1. Day 30: November 13, 2013 Memory Core: Part 2
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 30: November 13, 2013
Memory Core: Part 2
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2. Today
Multiport SRAM
More DRAM
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3. Memory Bank
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4. Multiport RAM
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5. Mulitport Perform multiple operations simultaneously
E.g. Processor register file
add r1,r2,r3
R3R1+R2
Requires two reads and one write
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6. Simple Idea
Add access transistors to 5T
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7. Watch? What do we need to be careful about?
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8. Adding Write Port
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9. Write Port
What options does this raise?
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10. Opportunity Asymmetric cell size Separate sizing constraints
Weak drive into write port (Wrestore)
Strong drive into read port (Wbuf)
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11. Multiple Read Ports What if want more than two read ports?
Can we do this again?
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12. Multiple Read Ports What should we be concerned about?
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13. Robust Read What makes more robust? Sizing impact?
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14. Isolate BL form Mem How make this work? Sizing impact?
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15. Isolate BL form Mem Larger, but more robust Precharge
Essential for large # of read ports
Precharge
ReadData High
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16. Multiple Write Ports How about multiple write ports?
Assuming at most one write per word
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17. Multiple Write Ports
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18. DRAM
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19. Some Numbers (memory) Register as stand-alone element (14T)  4Kl2
Static RAM cell (6T)  1Kl2
SRAM Memory (single ported)
Dynamic RAM cell (DRAM process)  100l2
Dynamic RAM cell (SRAM process)  300l2
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20. 1T 1C DRAM Simplest case – Memory is capacitor
Feature of DRAM process is ability to make large capacitor compactly
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21. DRAM Capacitors Sunami, Solid State Circuit, January 2008
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22. DRAM Trench Capacitor Sunami, Solid State Circuit, January 2008
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23. DRAM Capacitance Scaling
Sunami, Solid State Circuit, January 2008
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24. 3T DRAM
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25. 3T DRAM
How does this work?
Write?
Read?
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26. 3T DRAM Correct operation not sensitive to sizing
Does not deplete cell on read
No charge sharing with stored state
All NMOS (single well)
Precharge ReadData
Must use Vdd+VTN on W to write full voltage
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27. Energy
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28. Single Port Memory What fraction is involved in a read/write?
What are most cells doing on a cycle?
Reads are slow
Cycles long  lots of time to leak
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29. ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power
Isd,leak
100nA/mm
50pA/mm
Isd,sat
1200 mA/mm
560mA/mm
Cg,total
1fF/mm
0.91fF/mm
Vth
285mV
585mV
C0 = 0.045mm × Cg,total
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30. High Power Process V=1V d=1000 g=0.5 Waccess=Wbuf=2
Full swing for simplicity
Csc = 0
(just for simplicity, typically <Cload)
BL: Cload=1000C0 ≈ 45 fF = 45×10-15F
WN = 2  Ileak = 9×10-9 A
P= (45×10-15) freq ×9×10-9 W
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31. Relative Power P= (45×10-15) freq + 1000×9×10-9 W
Crossover freq<200MHz
How partial swing on bit line change?
Reduce dynamic energy
Increase percentage in leakage energy
Reduce crossover frequency
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32. Consequence Leakage energy can dominate in large memories
Care about low operating (or stand-by) power
Use process or transistors with high Vth
Reduce leakage at expense of speed
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33. Idea Memory can be compact Rich design space Demands careful sizing
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34. Admin Project 2 out Friday here for Memory Periphery Monday in Detkin
Milestone due Tuesday
Friday here for Memory Periphery
Monday in Detkin
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