Presentation is loading. Please wait.

Presentation is loading. Please wait.

Day 17: October 8, 2014 Performance: Gates

Published byClinton Skinner Modified over 5 years ago

Similar presentations

Presentation on theme: "Day 17: October 8, 2014 Performance: Gates"— Presentation transcript:

1 Day 17: October 8, 2014 Performance: Gates
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 8, 2014 Performance: Gates Penn ESE370 Fall DeHon

2 First Order Delay t = R0C0 = C0/I0
Previously: R0 = Resistance of minimum size NMOS device I0 = Ids of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/Wn Idrive = WI0 Cg = WC0 Technology independent relative delay t = R0C0 = C0/I0 Large fanout – drive in stages Penn ESE370 Fall DeHon

3 Today Delay in Gates Data Dependent Delay Large Fanin
Do everything for two cases: Rp0=Rn0 and Rp0=2Rn0 Penn ESE370 Fall DeHon

4 Gates Penn ESE370 Fall DeHon

5 Data Dependent Delay Resistance depends on input values
delay depends on input data t-delays assuming minsize? assume 2C0 load Penn ESE370 Fall DeHon

6 How Size How size to equalize worst-case rise/fall times for Rdrive=R0/2? Penn ESE370 Fall DeHon

7 Series Transistors Penn ESE370 Fall DeHon

8 How Size How size for equal rise/fall for Rdrive=R0/2?
Penn ESE370 Fall DeHon

9 Input Load Input capacitance per input in each case?
Penn ESE370 Fall DeHon

10 Observe Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids Differs with gate function Some gates give more drive per capacitive load we pay When Ids differ at same W Penn ESE370 Fall DeHon

11 How Size Size equalize rise/fall times Rdrive=R0/2?
Penn ESE370 Fall DeHon

12 Increasing Fanin What happens to input capacitance as fanin (k) increases Keeping output drive the same E.g. Rdrive=R0/2 k-input nand gate has what input capacitance? Penn ESE370 Fall DeHon

13 Fanin Conclude: gates slow down with fanin
Less drive per input capacitance Penn ESE370 Fall DeHon

14 Which is Fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2
Rn0=Rp0 case only nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Penn ESE370 Fall DeHon

15 Lesson Large gates are slow / inefficient
High capacitive load / drive strength Small gates can be inefficient Need many stages Staging over moderate size gates minimizes delay Exact size will be technology dependent Penn ESE370 Fall DeHon

16 Delay of each implementation?
Penn ESE370 Fall DeHon

17 Take Away? Penn ESE370 Fall DeHon

18 Ideas First order reason in t=R0C0 units
Gates have different efficiencies Drive strength per unit input capacitance Without velocity saturation Reason to prefer nand over nor With velocity saturation (short term), nands and nors are similar efficiency Large fanin and fanout slow gates Decompose into stages …but not too much Penn ESE370 Fall DeHon

19 Subversive Innovation
Admin HW 6 is out Friday – Fall Break Back on Monday Tuesday 11am Talk by Herman Schmit Subversive Innovation Penn ESE370 Fall DeHon

Download ppt "Day 17: October 8, 2014 Performance: Gates"

Similar presentations

Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.
Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line.
Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 16, 2013 Energy and Power.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 16, 2013 Energy and Power.
Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 39: December 6, 2013 Repeaters in Wiring.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 39: December 6, 2013 Repeaters in Wiring.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 15, 2014 Energy and Power.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 15, 2014 Energy and Power.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 13, 2014 Energy and Power.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 13, 2014 Energy and Power.
Logical Effort and Transistor Sizing Digital designs are usually expected to operate at high frequencies, thus designers often have to choose the fastest.

Logical Effort and Transistor Sizing Digital designs are usually expected to operate at high frequencies, thus designers often have to choose the fastest.
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: December 5, 2012 Transmission Lines.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: December 5, 2012 Transmission Lines.
Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 7: September 22, 2010 Delay and RC Response.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 7: September 22, 2010 Delay and RC Response.
Linear Delay Model In general the propagation delay of a gate can be written as: d = f + p –p is the delay due to intrinsic capacitance. –f is the effort.

Linear Delay Model In general the propagation delay of a gate can be written as: d = f + p –p is the delay due to intrinsic capacitance. –f is the effort.
Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 14, 2013 Energy and Power.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 14, 2013 Energy and Power.
Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 8: September 15, 2014 Delay and RC Response.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 8: September 15, 2014 Delay and RC Response.
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 19, 2011 Energy and Power.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 19, 2011 Energy and Power.
Day 16: October 6, 2014 Inverter Performance

Day 16: October 6, 2014 Inverter Performance
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 31, 2011 Pass Transistor Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 31, 2011 Pass Transistor Logic.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 23: October 24, 2014 Pass Transistor Logic:

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 23: October 24, 2014 Pass Transistor Logic:
Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 19, 2012 Ratioed Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 19, 2012 Ratioed Logic.
Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 12, 2012 Transistor Introduction.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 12, 2012 Transistor Introduction.

Similar presentations

Ads by Google