Day 33: November 19, 2014 Crosstalk ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 19, 2014 Crosstalk Penn ESE370 Fall2014 -- DeHon

Today Crosstalk How arise Consequences Magnitude Avoiding Penn ESE370 Fall2014 -- DeHon

Capacitance There are capacitors everywhere Already talked about Wires as capacitors Capacitance between terminals on transistor Penn ESE370 Fall2014 -- DeHon

Miller Effect For an inverting gate Capacitance between input and output must swing 2 Vhigh Or…acts as double-sized capacitor Penn ESE370 Fall2014 -- DeHon

Capacitance Everywhere Potentially a capacitor between any two conductors On the chip On the package On the board All wires Package pins PCB traces Cable wires Bit lines Penn ESE370 Fall2014 -- DeHon

Capacitor Dependence Decrease with conductor separation Increase with size Depends on dielectric Penn ESE370 Fall2014 -- DeHon

Parallel Wires Parallel-plate capacitance between wires Penn ESE370 Fall2014 -- DeHon

Wire Capacitance Changes in voltage on one wire may couple through capacitance to another Penn ESE370 Fall2014 -- DeHon

Consequences Qualitative First Penn ESE370 Fall2014 -- DeHon

Wire step response Step response for isolated wire? Penn ESE370 Fall2014 -- DeHon

Driven Wire What happens to a driven “victim” wire? One wire switches Neighbors driven but not switch What happens to neighbors? Penn ESE370 Fall2014 -- DeHon

Driven Wire Can this be a problem? What if victim is: Clock line Asynchronous control Non-clock used in synchronous system Outputs sampled at clock edge Penn ESE370 Fall2014 -- DeHon

Undriven Wire What happens to undriven wire? Where do we have undriven wires? Penn ESE370 Fall2014 -- DeHon

Clocked Logic CMOS driven lines Clocked logic Willing to wait to settle Impact is solely on delay May increase delay of transitions Penn ESE370 Fall2014 -- DeHon

Magnitude Quantitative Penn ESE370 Fall2014 -- DeHon

How large is the noise? V1 transitions from 0 to V? Penn ESE370 Fall2014 -- DeHon

How large is the noise? V1 transitions from 0 to V Penn ESE370 Fall2014 -- DeHon

Noise Magnitude Penn ESE370 Fall2014 -- DeHon

SPICE C1=10pF, C2=20pF Penn ESE370 Fall2014 -- DeHon

Good (?) Capacitance High capacitance to ground plane Limits node swing from adjacent conductors Penn ESE370 Fall2014 -- DeHon

Driven Line What happens when victim line is driven? Penn ESE370 Fall2014 -- DeHon

Driven Line Driven line Recovers with time constant: R2(C1+C2) Penn ESE370 Fall2014 -- DeHon

Spice: R2=1K, C1=10pF, C2=20pF Penn ESE370 Fall2014 -- DeHon

Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants t1<< t2 t1>> t2 t1~= t2 Penn ESE370 Fall2014 -- DeHon

Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants t1<< t2 full diversion, then recover t1~= t2 t1>> t2 Charge capacitor faster than line 1 can change little noise Penn ESE370 Fall2014 -- DeHon

Spice: C1=1pF, C2=2pF Penn ESE370 Fall2014 -- DeHon

Switching Line with Finite Drive What impact does the presence of the non switching line have on the switching line? All previous questions were about non-switching Note R on switching Penn ESE370 Fall2014 -- DeHon

Simultaneous Transition What happens if lines transition in opposite directions? Penn ESE370 Fall2014 -- DeHon

Simultaneous Transition What happens if transition in opposite directions? Must charge C1 by 2V Or looks like 2C1 between wires Penn ESE370 Fall2014 -- DeHon

Simultaneous Transition What happens if lines transition in same direction? Penn ESE370 Fall2014 -- DeHon

Simulation V2 switching at ¼ frequency of V1 No crosstalk reference case where no V2 Penn ESE370 Fall2014 -- DeHon

Crosstalk Victim Simulations Penn ESE370 Fall2014 -- DeHon

Victimization Setup Penn ESE370 Fall2014 -- DeHon

Crosstalk Victimization Simulation Penn ESE370 Fall2014 -- DeHon

Where Arise Penn ESE370 Fall2014 -- DeHon

Cables and PCB Wires Source; http://en.wikipedia.org/wiki/File:Flachbandkabel.jpg Penn ESE370 Fall2014 -- DeHon

Printed Circuit Board Source: http://en.wikipedia.org/wiki/File:Testpad.JPG Penn ESE370 Fall2014 -- DeHon

Interconnect Cross Section Image from Rabaey text, pg48, Fig2-7k ITRS 2007 38 Penn ESE370 Fall2014 -- DeHon 38

IC Metalization Source: http://en.wikipedia.org/wiki/File:Silicon_chip_3d.png Penn ESE370 Fall2014 -- DeHon

Standard Cell Area inv nand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html Penn ESE370 Fall2014 -- DeHon

Wires Will be capacitively coupled to many adjacent wires of varying degrees Penn ESE370 Fall2014 -- DeHon

bit lines, word lines wordline bitline Penn ESE370 Fall2014 -- DeHon Source: http://techon.nikkeibp.co.jp/article/HONSHI/20071219/144399/

Addressing Penn ESE370 Fall2014 -- DeHon

What can we do? How can we reduce? Penn ESE370 Fall2014 -- DeHon

What can we do? Orthogonal routing layers Widen spacing between wires Avoid parallel coupling vertically Widen spacing between wires Particularly critical path wires Limit length two wires run in parallel Separate with power planes Separate with ground/power wires Penn ESE370 Fall2014 -- DeHon

Idea Capacitance is everywhere Especially between adjacent wires Will get “noise” from crosstalk Clocked and driven wires Slow down transitions Undriven wires voltage changed Can cause spurious transitions Penn ESE370 Fall2014 -- DeHon

Admin In lab on Friday Project due Tuesday Please read lab handout in advance Project due Tuesday Penn ESE370 Fall2014 -- DeHon