1. 1 Interconnect/Via

2. 2 Delay of Devices and Interconnect

3. 3 Reduction of the feature size Increase in the influence of the interconnect delay on system performance The difference in the arrival times of the clock signal to all registers in a synchronous digital system Skew

4. 4 PowerPC microprocessor 32,000 master/slave latch An Example, The Clock Distribution Network ( CDN ) A set of interconnections that delivers reliably a time reference, clock signal, to every register element in a synchronous digital system.

5. 5 Memory Leakage Short-Circuit Clock I/O Global Interconnect Logic and Local Routing Power Consumption &Routing and system complexity P= CV 2 f

6. 6 Delay model of the CDN, Elmore Delay model r1r1 r2r2 s1s1 r4r4 r3r3 s2s2 s0s0 It takes into account the interconnect resistance and capacitance and the capacitance of the registers ec 0/ /2 er 0 ec 0/ /2 s1s1 r1r1 r2r2 s2s2 r3r3 r4r4 s0s0

7. 7 Out In RiRi RjRj TiTi TjTj T PD(min) /T PD(max) Example: Routing delay problems The Clock Skew The difference between time arrivals of the clock signal to all the registers in a synchronous digital system S(ij) = T i - T j Clock Period Limitations Permissible range Race Conditions S(ij) min S(ij) max S(ij)  T HOLDj - T PD(min) S(ij)  T clk - T PD(max) Two conditions:

8. 8 Minimizing the effects of delay, The H_Tree If it is possible to divide the set of registers R into two symmetric sets recursively and alternatively by vertical and horizontal lines, then the set R can be connected by an H-tree

9. 9 Interconnect Length

10. 10 Interconnect/Via

11. 11 Cross Section View of Capacitances in interconnect Units are in Angstrom, 1A=0.1nm

12. 12 Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application

13. Small line length: transistor speed governs the circuit speed. Medium line length Transistor output resistance and line capacitance govern the circuit speed. Long line length, line resistance and line capacitance govern the circuit speed. Cooling the room temperature to 77K reduces the resistivity by an order of magnitude. At higher frequencies, Ghz and above the skin effect has to be taken into account.

14. Local interconnect are used for short distances on the chip. Mainly to connect the device Drain, source, gates or immediate devices. Semi_global interconnect is used to connect gates FFs other small devices within a block of the hierarchy. Global wiring is used for long interconnect such as Clock signal or other control signals. Separating the interconnect wires and the devices from each other are the dielectric material. The dielectric material gets thicker as move higher in the hierarchy of the wire placement Interconnect usage

15. 15 Parallel and fringing Capacitance

16. http://maxwell.ucdavis.edu/~electro/dc_circuits/capacit ance.html Fringing Capacitance

17. 17 Fringing Capacitance T is the thickness of wire H is the distance of wire to substrate.

18. 18 Cross Talk

19. Cross talk Is a disturbance caused by the electric or magnetic fields of one telecommunication signal affecting a signal in an adjacent circuit. Two effects: increased capacitance on the driver. Introduction of unwanted signal or noise from one line to the other. Design tips: Methods to reduce cross talk, Increase inter_wire spacing. Place Vdd or ground wires between signal lines.

20. 20 Fringing/ Parallel Plate Capacitance of Interconnect

21. 21 Modeling Interconnect LUMPED MODEL T-MODEL -MODEL 2T-MODEL 2π -MODEL

22. 22 Modeling of Interconnect

23. 23 Delay of Interconnect Capacitance = C/unit area * L (length) * W (width) = C Resistance = R/ * number of squares = R

24. Delay comparison 24

25. RC delay with distributed parameters: More accurate than lumped RC model More difficult to solve for large N Need full-scale SPICE simulation

26. 26 Example A signal is propagated on a 6mm length metal 1 (M1) interconnect of CMOSIS5 Process, using minimum wire width. Calculate the delay and comment on methods for reducing this delay. 6mm

27. Rent’s rule, relates number of i/O pins T, to the number of gates N in a random logic network: T=kN**p Where: k = average I/O per gate P= Rent’s exponent. It reflects wiring complexity, p=1 is the highest. T

28. 28 What is the maximum size of silicon chip? Power dissipation Packaging Number of pins Technology The interconnect used

29. 29 Thank you !

30. 30 Inductances For die wires h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material

31. 31 Inductance For on-chip, h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material

32. 32 Ground Bounce and Vdd Sag examples from Alterahttp://www.altera.com/literature/wp/wp_grndbnce.pdf

33. 33 Example on V DD Bounce Determine the values of due to inductive and resistive losses when the output driver sources 10mA in 1.5ns in the following circuit. Assume inductance of 13.9nH/mm.

34. 34 Circuit Vdd Circuit Gnd Board Gnd Board Vdd

35. 35 Example on Power lines What will be the power line width if you drive a 10pF load at 1GHz Assume Vdd=3.5V.

36. 36 Example on Charge Sharing Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances. Assume bus capacitance to be 10pF.

37. 37 Thank you !