1. Day 38: December 4, 2013 Transmission Lines Implications
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 38: December 4, 2013
Transmission Lines
Implications
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2. Transmission Line Agenda
Where arise?
General wire formulation
Lossless Transmission Line
See in action in lab
Impedance
End of Transmission Line?
Termination
Implications
Discuss Lossy
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3. Transmission Line Data travels as waves Line has Impedance
May reflect at end of line
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4. Series Termination
What happens here?
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5. Simulation
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6. Series Termination Rseries = Z0 Initial voltage divider
Half voltage pulse down line
End of line open circuit
sees single transition to full voltage
Reflection returns to source and sees termination Rseries = Z0
No further reflections
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7. Termination Cases Parallel at Sink Series at Source
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8. CMOS Driver / Receiver
Driver: What does a CMOS driver look like at the source?
45nm
Receiver: What does a CMOS inverter look like at the sink?
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9. Some Transmission Lines
Characteristics arise form their geometry
(don’t expect you to know these equations – look them up [or given])
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10. Coaxial Cable Inner core conductor: radius r
Insulator: out to radius R
Outer core shield (ground)
RG-58 Z0= 50W – networking, lab
(RG-59 Z0= 75W – video)
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11. Printed Circuit Board Stripline Trace between planes w b t er
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12. Printed Circuit Board Microstrip line Trace over single supply plane wh er
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13. Twisted Pair Category 5 ethernet cable 100W V=0.64c0
Source:
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14. (you should be able to reason about this)
Implications
(you should be able to reason about this)
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15. Example 25meter category-5e cable (100W, 0.64c)
Supporting 1Gb/s ethernet
4 pairs at 250Mb/s
Time to send data from one end to the other?
Time between bits at 250Mb/s?
Bits in the cable?
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16. Pipeline Bits For properly terminated transmission line
Do not need to wait for bits to arrive at sink
Can stick new bits onto wire
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17. Limits to Bit Pipelining
What limits? (why only 250Mb/s)
Risetime/distortion
Clocking
Skew
Jitter
For bus
Wire length differences between lines
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18. Eye Diagrams Watch bits over line on scope Look at distortion
“open” eye clean place to sample
Consistent timing of transitions
Well defined high/low voltage levels
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20. Termination / Mismatch
Wires do look like these transmission lines
We are terminating them in some way when we connect to chip (gate)
Need to be deliberate about how terminate, if we care about high performance
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21. Where Mismatch? Vias Wire corners? Branches Connectors Board-to-cable
Cable-to-cable
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22. Lossy Transmission Line
How do addition of R’s change?
Concretely, discretely think about R=0.2W every meter on Z0=100W
what does each R do?
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23. Lossy Transmission Line
R’s cause signal attenuation (loss)
Voltage divider R Z0
Reduced signal swing at sink
Limits length of transmission line before need to restore signal
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24. Impedance Change
What happens if there is an impedance change in the wire? Z0=75W, Z1=50W
What reflections and transmission do we get?
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25. Z0=75, Z1=50 At junction: Reflects Transmits Vr=(50-75)/(50+75)Vi
Vt=(100/(50+75))Vi
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26. Impedance Change Z0=75, Z1=50
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27. What happens at branch?
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28. Branch Transmission line sees two Z0 in parallel Looks like Z0/2
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29. Z0=50, Z1=25 At junction: Reflects Transmits Vr=(25-50)/(25+50)Vi
Vt=(50/(25+50))Vi
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30. End of Branch What happens at end?
If ends in matched, parallel termination
No further reflections
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31. Branch Simulation
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32. Branch with Open Circuit?
What happens if branch open circuit?
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33. Branch with Open Circuit
Reflects at end of open-circuit stub
Reflection returns to branch
…and encounters branch again
Send transmission pulse to both
Source and other branch
Sink sees original pulse as multiple smaller pulses spread out over time
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34. Open Branch Simulation
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35. Open Branch Simulation
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36. Bus Common to have many modules on a bus
Bus
Common to have many modules on a bus
E.g. PCI slots
DIMM slots for memory
High speed  bus lines are trans. lines
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37. Multi-drop Bus Ideal Open circuit, no load
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38. Multi-Drop Bus Impact of capacitive load (stub) at drop?
If tight/regular enough, change Z of line
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39. Multi-Drop Bus Long wire stub? Looks like branch
may produce reflections
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40. Transmission Line Noise
Frequency limits
Imperfect termination
Mismatched segments/junctions/vias/connectors
Loss due to resistance in line
Limits length
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41. Idea Transmission lines Termination Signal quality high-speed
high throughput
long-distance signaling
Termination
Signal quality
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42. Admin HW8 due Thursday Last Andre lecture Friday
Spencer Review Monday (12/9)
Final (12/13) noon Towne 307
Real Genius (Saturday 12/14 2pm)
Levine 307
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