1. Day 29: November 10, 2014 Memory Core: Part 1
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 29: November 10, 2014
Memory Core: Part 1
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2. Today 5T/6T SRAM DRAM Writing Charge sharing Precharge
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3. Memory Bank
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4. 5T SRAM Memory Bit
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5. Write (preclass 1)
Assuming properly select only one WL, what does write circuit look like?
What transistors are ON when writing a 0 over a cell that holds a 1?
Drive with inverter at BL
Width Wwrite
Voltage written? 1V
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6. Write (preclass 1)
Assuming properly select only one WL, what does write circuit look like?
Voltage written? 1V
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7. Write Conclude? Writing into cell is a ratioed operation.
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8. Write (preclass 2)
Assuming properly select only one WL, what does write circuit look like?
How different when writing a 1 over a cell holding a 0 ? 1V
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9. 6T Cell How does 6T make it easier to perform writes?
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10. Preclass 3 Initially Close switch Voltage at A? A @ 1V B @ 0V
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11. Preclass 3 Initially QA=1V*C1=C1 Close switch Qtot=Vfinal*(C1+C0)0V
QA=1V*C1=C1
Close switch
Qtot=Vfinal*(C1+C0)
Charge conservation
QA=Qtot
C1=Vfinal*(C1+C0)
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12. Consider (preclass 4)
Read: What happens to voltage at A when WL turns from 01?
Assume Waccess large
Waccess >> Wpu=1
BL initially 0
A initially 1
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13. Voltage After enable Word Line
QBL = 0
QA = (1V)(g(2+Waccess)C0)
CBL>>CA=(g(2+Waccess)C0)
After enable Waccess (Waccess large)
Total charge QBL +QA roughly unchanged
Distributed over larger capacitance~=CBL
VA=VBL~= CA/CBL
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14. Larger Resistance? What happens if Waccess small? Waccess < Wpu
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15. Larger Resistance? What happens if Waccess small?
Waccess < Wpu
Takes time to move charge from A to BL
Moves more slowly than replished by pu
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16. Simulation: Waccess=100
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17. Simulation
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18. Charge Sharing Conclude: charge sharing can pull down voltage
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19. Consider What happens to voltage at A when WL turns from 01?
Assume Waccess large
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20. Simulation Waccess=20
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21. Simulation Waccess=4
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22. Charge Sharing Conclude: charge sharing can lead to read upset
Charge redistribution adequate to flip state of bit
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23. How might we avoid?
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24. Charge to middle Voltage
Charge bitlines to Vdd/2 before begin read operation
Now charge sharing doesn’t swing to opposite side of midpoint
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25. Pre-Charge
Use one phase of clock to charge a node to some initial value before operation
Precharge
Transistor
Can be
large
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26. Simulation Waccess=20
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27. Compare
Both Waccess=20; vary precharge
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28. Simulation Waccess=20 (precharge Vdd/2, reading 0)
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29. Simulation Waccess=20 (with precharge Vdd/2)
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30. Pre-Charge
Use one phase of clock to charge a node to some initial value before operation
Precharge
Transistor
Can be
large
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31. 5T/6T SRAM Questions?
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32. Idea Memory can be compact Demands careful sizing
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33. Admin HW7 due tomorrow Project 2 out Due 2 weeks from tomorrow
Tuesday before Thanksgiving
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