1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 3/22/2006 Functional Blocks and Simulation Design Manager: Abhishek Jajoo

2Status  Design Proposal  Project chosen: 16 bit Delta-Sigma ADC  Basic specs defined  Architecture  Matlab Simulated  Behavioral Verilog - Simulated  Structural Verilog – Simulated  Schematic  Digital – All modules created  Analog - All modules created  Floorplan  Revised for signal routing  Layout  Op Amps – DRC, LVS, Simulated  Low Pass Filter – DRC, LVS, Simulated  PII – DRC, LVS, Simulated  Sinc Filter – DRC, Not LVS, Not Simulated  Simulation / Verification  All modules verified separately at transistor level and some layouts

3 Analog Progress Everything is in Transistor Level and Verified Everything is in Transistor Level and Verified Layouts and Extracted Views of the Operational Amplifiers Layouts and Extracted Views of the Operational Amplifiers Integrator - Verified Integrator - Verified Comparator – Verified Comparator – Verified Reviewed Common Centroid Style of Layout Reviewed Common Centroid Style of Layout More in-depth next week… More in-depth next week…

4 Design Decisions Metal Directionality Metal Directionality Buffering – Clock to Minimize Glitching Buffering – Clock to Minimize Glitching Overall Chip Routing and Signal Directionality Overall Chip Routing and Signal Directionality Compacted Mirror-adder and DFF Compacted Mirror-adder and DFF Reviewed Common Centroid Layout – Next Week… Reviewed Common Centroid Layout – Next Week…

5 Clock Buffering

6 DFF Layout

7 DFF Simulations

8 Mirror Adder Layout

9 Mirror Adder Simulations

10 24-Bit Counter Layout

11 24-Bit Counter Simulations

12 12-Bit Equality Function - Layout

13 12-Bit Equality Function Simulations

14 12-Bit Register - Layout

15 12-Bit Register Simulations

16 PII Function - Layout

17 Sinc Filter -Layout

18 Timing and Power Total = 6,432 transistors, uW of power BlockPowerDelayTransistors 16-Bit Adder22.47uW at 5.12MHz2.856ns Bit Subtractor28.54uW at 5.12MHz 13.09uW at 20KHz 2.916ns Bit Register22.41uW at 20KHz1.065ns Bit Register33.17uW at 5.12MHz 29.88uW at 20KHz 1.065ns Bit Equality Function3.323uW at 20KHz270.5ps Bit Multiplexer2.114uW at 20KHz24.7ps96 Clock Divider4.812uW241.5ps334 2nd order Sinc Filter227.1uW8.748ns3296 PII Function115.9uW2.950ns2782 Decimator347.8uW8.748ns6412 Analog Op-Amps162uW Total (81 uW each) N/A11 for Integrator, 9 for Comparator

19Floorplan

20 Problems and Questions Layout is very time consuming Layout is very time consuming More metal layers or larger layouts? More metal layers or larger layouts? Sand in my laptop Sand in my laptop

21 What's Next… LVS all blocks LVS all blocks Sinc Filter Sinc Filter Analog Components Analog Components Global Routing Global Routing Wire Decimation filter and Modulator Wire Decimation filter and Modulator Wire Overall Chip Wire Overall Chip Overall Chip Simulation Overall Chip Simulation Extract and simulate in a mixed signal env. Extract and simulate in a mixed signal env. Optimization Optimization