1. Noise Canceling in 1-D Data: Presentation #9 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Mar 23 rd, 2005 Full chip LVS Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (85%) –Spice simulation

3. Design Decisions Redesigned the horizontal FP Adder to be more similar to vertical floorplan Redesign buffers  H-tree buffer to facilitate abutment with other cells Placement of AND gates and Mirror Adders in the Wallace tree

4. Last Week’s Floorplan

5. Current Floorplan

6. Old vs. New FP Multiplier (A)

7. Wallace Layout (old buffers)

8. Wallace layout (new buffers)

9. Old vs. New FP Adder (vertical)

10. FP Adder (old horizontal)

11. Floating Point Adder (horizontal)

12. Challenges… Finishing up layout Make sure that the signal strength is sufficient (buffering) Global wiring Shrinking functional blocks (white space)

13. Questions?