1. Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery Sean Baker Huiyi Lim Huiyi Lim Sherif Morcos Amar Sharma Date: 1/25/2006 Design Proposal

2. Why DVP-525? Customers in Pain Customers in Pain Government and Security Agencies Government and Security Agencies Hearing Aid Owners Hearing Aid Owners Digital Voice Providers Digital Voice Providers Vonage, Skype, and CRM Vonage, Skype, and CRM Impact On Customers Impact On Customers Secure Private Telephony Secure Private Telephony Custom Hearing Aids for Specific Conditions Custom Hearing Aids for Specific Conditions Better-Cheaper Telephone Service (VOIP) Better-Cheaper Telephone Service (VOIP) More Accurate Speech to Text More Accurate Speech to Text

3. Applications Any Communication Device Any Communication Device Encrypted Digital Telephony Encrypted Digital Telephony Digital Hearing Aids Digital Hearing Aids Voice Over IP Voice Over IP Speech Recognition Speech Recognition

4. Alternative Project Ideas Shoe Odometer Shoe Odometer Digital Equalizer Digital Equalizer ADC Health Monitor ADC Health Monitor Multi-Single Channel Audio Converter Multi-Single Channel Audio Converter Video Over CAT-5 Video Over CAT-5 SMART Smoke Detector SMART Smoke Detector Auto Swiss Army Knife Auto Swiss Army Knife

5. Design Breakdown Overall Design Analog Design 2 nd Order Delta Sigma Modulator Integrator Comparator Low Pass Filter Digital Design Decimator Low Pass Filter Noise Cancellation Filter Sync Filter

6. Overall Chip Block Diagram Sample Delta Sigma Analog to Digital Converter

7. Transistor Estimate Analog Analog 4 x Analog Op Amps, 4 x 24 = 96 4 x Analog Op Amps, 4 x 24 = 96 Capacitive Resistive Elements Capacitive Resistive Elements Digital Digital 5 x 8-bit Adder, 5 x 2300 = 11500 5 x 8-bit Adder, 5 x 2300 = 11500 3 x 8-bit Multiplier, 3 x 2100 = 6300 3 x 8-bit Multiplier, 3 x 2100 = 6300 1 x 8-bit Divider, 1 x 4800 = 4800 1 x 8-bit Divider, 1 x 4800 = 4800 Total Transistors 23,176 (~9,300 Design) Total Transistors 23,176 (~9,300 Design)

8. Design Decisions Chose Delta-Sigma Modulator Chose Delta-Sigma Modulator Continuous Time instead of Discrete Continuous Time instead of Discrete Decimator Decimator Digital Low Pass – 8-Bit Output Digital Low Pass – 8-Bit Output 3-5 Stage Sync Filter 3-5 Stage Sync Filter Multiplier/Divider/Adder Multiplier/Divider/Adder Non-floating point Non-floating point 16-Bit Output 16-Bit Output

9. Problems and Questions What is minimum clock speed to work? What is minimum clock speed to work? 20Hz to 20KHz @56Kbit/s 20Hz to 20KHz @56Kbit/s Complexity of Modulator/Decimator Complexity of Modulator/Decimator 2 nd Order instead of 1 st Order? 2 nd Order instead of 1 st Order? Stability of Modulator – Ideal Op Amp Stability of Modulator – Ideal Op Amp # of Stages for Decimator # of Stages for Decimator Possibility of Last Stage Function Possibility of Last Stage Function …. Are we Crazy? …. Are we Crazy?