1. Sprinkler Buddy Presentation #6: “Optimized Schematics and Component Layout” 2/28/2007 Team M3 Devesh Nema Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Design Manager: Bowei Gai “Low Cost Irrigation Management For Everyone ! ”

2. Current Status Determine Project Develop Project Specifications Plan Architectural Design Determination of all components in design Detailed logical flowchart Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout (big comp. finished…~ 40 % of whole done) Testing (Extraction, LVS, and Analog Sim.) (ongoing…)

3. Last Week’s Floor Plan

4. Current Floor Plan

5. Individual Modules: BlockMetal Layers That Have Been Used 40:20 MuxesM1 & M2 60:20 MuxesM1 & M2 CountersM1 & M2 KC ROMM1 & M2 & M3 & M4 P ROMM1 & M2 & M3 & M4 Metric Storage SRAMSM1 & M2 & M3 & M4 Constant Storage ROMM1 & M2 & M3 & M4 Floating Point AddersM1 & M2 & M3 Floating Point Multipliers M1 & M2 & M3 & M4 10 Bit RegistersM1 & M2 & M3

6. Transistor Count … Block (# used)Old TCNew TC 40:20 Muxes (6)~480362 60:20 Muxes (2)~720644 Counter (2)~250220 KC ROM (1)~7781256 P ROM (1)~82122 Metric Storage SRAMS (2) ~25222430 Constant Storage ROM (1) ~202428 Floating Point Adder (4) ~30003210 Floating Point Multiplier (2) ~28001398 10 Bit Registers (9) ~140210 Datapath Logic / Misc. ~20002305 Total = 30,397

7. New Design Size Block (# used)Size Estimate (um) 40:20 Muxes (4)20 x 80 60:20 Muxes (2)20 x 120 Counter (2)12 x 17 KC ROM (4 parts)181 x 8 P ROM (1)70 x 8 Metric Storage SRAMS (2) 181 x 60 Constant Storage ROM (1) 181 x 8 Floating Point Adder (4) 96x151 Floating Point Multiplier (2) 130 x 60 10 Bit Registers (8)50 x 10 464um x 416 um ~ 1 : 1.11 aspect ratio.193 mm^2 area.16 Transistor Density

8. FSM Logic in Schematic

9. Schematics: Read to SRAM

10. Schematics: Write to SRAM

11. Layout : SRAM

12. Layout : Adders and Multipliers 14 T Full Adder Multiplier

13. Layout : Flip Flops

14. Folding of Transistors

15. Design Challenges and Implementation Decisions For The Past Week Design Challenge Translation to HW Low Power Design Finalized 14 T Full Adder Design Optimally Sized All Gates Minimal Usage of OR/NOR Gates

16. Problems/Questions We need to generate an XOR which matches the width of a Full Adder Need to finalize the layout of control logic around other blocks

17. For Next Week Lots and Lots of Layout Wiring inside main components (FP units) FSMs Global Routing