1. 1 Team M1 Enigma Machine Milestone 10 - 17 April, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka

2. 2 Status Finished: Functional definition and simulation Schematic and simulation/verification Top level modules (except SRAM) Module DRC and LVS (except SRAM) Updated floorplan Final transistor count (except SRAM) In Progress: SRAM goes here. Global Layout To Do: Top level LVS Simulation/verification

3. 3 Design Decisions Floorplan… revised to fit the final module layouts. !!!Time Accommodations!!! SRAM: Rather than building a custom decoder for the SRAM, we will use the decoder from the 26-bit ROM, which is functionally the same but not optimized for space. ROM Layout: ROM is not as compact as it could be. Serial input registers: Will not have the ‘fingers’ fixed. Floorplan: Not as compact as it could be. I.E. It’s better to get it working then optimize a broken design.

4. 4 New Floorplan Results Good news!!! Floorplan is relatively close to the original plan. We saved a lot of space… the ROMs were a lot more compact than we had planned for. Estimated Floorplan: 271 x 248 New Floorplan: 198 x 251 Actually helped with wiring… the new blocks fit together closer to their main connection than in the original plan.

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6. 6 Wheelreg_serialin Wheelcounters Fsm Adder_mod26 Reg3bx8 serialin rom208 RAM rom26 RAM

7. 7 Wheelreg_serialin Wheelcounters Fsm Adder_mod26 Reg3bx8 serialin rom208 RAM rom26 RAM

8. 8 Wheelreg_serialin Wheelcounters Fsm Adder_mod26 Reg3bx8 serialin rom208 RAM rom26 RAM

9. 9 Transistor Count Module:Initial:Final: Muxes550270 RAM11501462 ROM4700 (oops)1626 Adder450298 Registers800 (w/o serial in)1904 Counters1250 (oops)2746 FSM300441 Totals:92008747

10. 10 ROM Layout ROM is a NAND ROM design. ROM was initially two rows of 208 x 5bits. In planning this was way too high, so… Broke it into four rows of 104 x 5bits and use a mux to choose from outputs. More than halves the capacitance of the bit line Increases the bits on each word line, but this is easy to fix with larger driving buffers.

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13. 13 … and the smaller ROM Used for the wheel reflectors Only 26 x 5 bits.

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15. 15 SRAM Progress SRAM cell is done and verified. Cell array is built. Decoder is built (from 26-bit ROM), but needs to be connected. Controlling counter (5-bits, stops at 25) is being modified from the 5-bit mod26 counter. Should be finished Tuesday. Global layout continues in parallel.

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17. 17 Sleep is for losers. Plan of action: Step 1: Go out and buy (3 people * 7 days * 2) = 42 liters of Mountain Dew™. Step 2: Step 3: Profit from amazing new encryption chip that will be LVS’d by next week.

18. 18 Questions Anyone finished with their design want to get some more practice with layout?