1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage VI: February 25 h 2004 COMPONENT SIMULATION Presentation #6: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Schematic Design (Fixed)  Input/Output Logic to SBOX Changed and Tested  Top Level Schematic Verified – Pipeline Works!  Layout  Component Layout (Done—Continually Changing)  Simulations (50% Due to Changes in Major Blocks)  To be Done  Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Design Decisions & Problems DECISIONS Removed XORs from hardcoded values found within: Round Permutation  MixCol  XTime Key Expand Changed ROM to allow for Precharging NMOS Pass-Gates Added to Inputs of ROM: Gate Tied to Clock Added Input and Output Flip-Flops to keep a clean signal PROBLEMS Need to Size Gates More Aggressively ROM DFF XOR (Implemented Using Pass-Transistors!) New Layout of Components Need to Be Finalized—Can’t change them everyday! 18-525 Integrated Circuit Design Project

4. ELIMINATION - Eliminate 5 rounds - Eliminate 1 SBOX & control logic - Reduce transistor count to 27k 18-525 Integrated Circuit Design Project Old Schematic (10 Rounds)

5. New Schematic (5 Rounds) Mux used in both In and Out logic, moved outside and shared

6. Verilog Simulation Results e0 34 e7 8b 18-525 Integrated Circuit Design Project

7. Schematic Simulation Results Problems! 18-525 Integrated Circuit Design Project

8. Schematic Simulation Pipelined! ~One Output Per Clock Cycle~ 18-525 Integrated Circuit Design Project reg [4:0] counterx; always #5 clk = ~clk; initial begin counterx = 0; end always@(posedge clk) begin counterx = counterx + 1; if (counterx == 21) begin counterx = 0; end end initial begin clk = 1'b1; rst = 1'b1; #10 rst = 1'b0; #10 rst =1; @(posedge valid_in); text_in1[31:0] = 32'h00000000; // Expected: 1B3E9EDF key1[31:0] = 32'hFB473859; vin = 1; @(posedge valid_in); key1[31:0] = 32'b00000000000000000000000000000000; text_in1[31:0] = 32'h08f273e6; // Expected: 2DF5C18E vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h10174E72; // Expected: 87FE42E7 vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h30C42168; // Expected: 0BD9AFAC vin = 1; @(posedge valid_in); key1[31:0] = 32'h2F764A41; text_in1[31:0] = 32'h00000000; // Expected: 43B28B72 vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h91f0aca1; // Expected: c913f5ed vin = 1; @(posedge valid_in); key1[31:0] = 32'h851b64d9; text_in1[31:0] = 32'h00000000; // Expected: 30d0299b vin = 1; @(posedge valid_in); key1[31:0] = 32'hc0000000; text_in1[31:0] = 32'h00000000; // Expected: ec4b0b60 vin = 1; @(posedge valid_in); key1[31:0] = 32'hfff80000; text_in1[31:0] = 32'h00000000; // Expected: b3adb97e vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h9b0cb284; // Expected: 69551ee1 vin = 1; #10000 $finish; end

9. Old Floorplan 18-525 Integrated Circuit Design Project ROM and Control Key Expand no pipe In Logic & Out Logic Round Permutations Key Expand Text & Key Output 345 um x 325 um

10. Updated Floorplan 325 um x 330 um Metal 3 Metal 2 Metal 1 Metal 4 SBOX and Control Logic Text DFFs and Add Round Key 5 th Round Key Expand Input to SBOX Logic & Select Output and Input Logic 4 Rounds of Key Expand 4 Rounds of Round Permutation Input/Output Logic CLK Divider Select & Input Logic SBOX and Control Logic Final Text Out Key DFFs and Input Logic

11. Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2

12. Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2 Multiple Metal 4 Direction (Where Things Have Already Been Wired Up – No Global Routing)

13. Updated Floorplan 325 um x 330 um Key[32] Text[32] Metal 3 Metal 2 Multiple Metal 4 Direction (Where Things Have Already Been Wired Up – No Global Routing) Output

14. ROM Schematic 18-525 Integrated Circuit Design Project

15. ROM Control with PMOS 18-525 Integrated Circuit Design Project

16. Old ROM and Control Logic 18-525 Integrated Circuit Design Project ROM Control Logic

17. New ROM and Control Logic (New Row of NMOS: Gates Tied to Clock to Control Inputs—Allows Precharging) 18-525 Integrated Circuit Design Project ROM Control Logic

18. Round Permutation 18-525 Integrated Circuit Design Project

19. Old Round Permutation 18-525 Integrated Circuit Design Project

20. Updated: Round Permutation 18-525 Integrated Circuit Design Project DFFsXORs Inputs

21. Key Expand 18-525 Integrated Circuit Design Project

22. Key Expand Layout (Will Be Changed) 18-525 Integrated Circuit Design Project Inputs (M2 Down, M3 Across) Outputs (M4) DFFs 1 st Level XORs

23. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project 8 x Mux5 Previous Logic To ROM

24. SBOX Select Tree In-Logic 18-525 Integrated Circuit Design Project Current Logic

25. SBOX Select Tree In-Logic 18-525 Integrated Circuit Design Project Current Logic Tree Structure Difficult to Implement in Layout Needed to finalize wiring from other modules in order to be more efficient in arranging in-logic Now: Decided to put next to its corresponding stage

26. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project Current Logic

27. SBox Mux Tree Out-Logic 18-525 Integrated Circuit Design Project

28. Changes To… XTime (Found in MixCol of RoundPermutations) 18-525 Integrated Circuit Design Project

29. Changes To… XTime (Found in MixCol of RoundPermutations) 18-525 Integrated Circuit Design Project 5XORs * 2 XTime per MixCol * 2 MixCol Per Round * 4 Rounds = 80 XORs

30. Changes To… KeyExpand (The Hardcoded RCON Value) 18-525 Integrated Circuit Design Project

31. Changes To… KeyExpand (The Hardcoded RCON Value) One Row of XORs Eliminated 18-525 Integrated Circuit Design Project 16 XORs per KeyExpand * 5 KeyExpands = 80 XORs

32. Waves D-FlipFlop Layout 18-525 Integrated Circuit Design Project

33. Waves D-FlipFlop Propagation Time 18-525 Integrated Circuit Design Project 624.832 ps

34. Waves D-FlipFlop Rise Time 18-525 Integrated Circuit Design Project 1.08073 ns

35. Waves D-FlipFlop Fall Time 18-525 Integrated Circuit Design Project 1.15726 ns

36. Waves XOR Propagation Time 18-525 Integrated Circuit Design Project 174.371 ps

37. Waves XOR Rise Time 18-525 Integrated Circuit Design Project 245.367 ps

38. Waves XOR Fall Time 18-525 Integrated Circuit Design Project 205.155 ps

39. Waves 4-XOR Propagation Time 18-525 Integrated Circuit Design Project 751.512 ps

40. Waves ROM Propagation Time 18-525 Integrated Circuit Design Project 869.757 ps

41. Waves ROM Control Propagation Time 18-525 Integrated Circuit Design Project 124.267 ps

42. Waves ROM Control Fall Time 18-525 Integrated Circuit Design Project 215.59 ps

43. Waves Longest Logic Path (Not Including ROM) 18-525 Integrated Circuit Design Project 762.727 ps

44. Current Speed Estimation 200 MHz 18-525 Integrated Circuit Design Project

45. COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 80 um x 40 um x 4 um + 35 um x40 um = 14,200 um 2 ROM  SBOX and Control Logic (2) 60 um x 250 um x 2 = 30,000 um 2 Transformation  Register & XORs 70 um x 70 x 4 = 19,600 um 2 Add Round Key & Final Text Out 70 um x 15 um x 2 = 2100 um 2 Others  Buffers & Wiring 10% = 6,590 um 2 CURRENT AREA DIMENSIONS Total: 330 um x 325 um (taken from current floorplan)

46. Current Transistor Count with 5 Rounds of Encryption (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (5) 136  SBoxMuxTreeIn (Text) 2336  SBoxMuxTreeIn (Key) 1056  SBoxMuxTreeOut (Text) 3992  SBoxMuxTreeOut (Key) 2038  ROM with New Control Logic (3) 7332  Key Expansion (5) 1920  Round Permutation (4) 5312  Final Text Out 256 Total: 24799 Total with Buffer Estimate (10%) 27278 New Total: (From LVS) 25, 237 18-525 Integrated Circuit Design Project

47. Questions?