1. 1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 2/22/2006 Top-Level Integration Design Manager: Abhishek Jajoo

2. 2Status  Design Proposal  Project chosen: 16 bit Delta-Sigma ADC  Basic specs defined  Architecture  Matlab Simulated  Behavioral Verilog - Simulated  Structural Verilog – Simulated  Schematic  Digital – All modules created  Analog - More accurate model created  Floorplan  Revised floorplan due to change in design  Working to get accurate reduced values  Layout  Intend to Bit Slice Sinc Filter but not the PII  Simulation / Verification  All modules verified separately

3. 3 Algorithm Detail Decimation (Sinc Filter, Downsample) Measure Peak Amplitude (Peak Input Indicator) Digital Output Digital Peak Indicator Analog Input Lowpass Filter Analog to Digital Conversion (Delta-Sigma Modulator) Analog

4. 4 Analog Design Progress Decided upon RC values for Low Pass Filter Decided upon RC values for Low Pass Filter Decided Operational Amplifier Topologies Decided Operational Amplifier Topologies Modified Behavioral Schematic to more accurately model the desired real circuit. Modified Behavioral Schematic to more accurately model the desired real circuit.

5. 5 Low Pass Filter Requirement for a low pass filter before passing through Delta-Sigma Modulator Requirement for a low pass filter before passing through Delta-Sigma Modulator Passive Filter Passive Filter - only resistors and capacitors - only resistors and capacitors Butterworth Filter Butterworth Filter - as opposed to Chebyshev Filter - as opposed to Chebyshev Filter

6. 6 Butterworth Filter Chebyshev Filter

7. 7 …a little more about Butterworth Filters

8. 8 if we use a second order Butterworth Filter… R = 100K  R = 100K  >>120μm^2 >>120μm^2 >> 2 Resistors >> 2 Resistors C = 2.2nF C = 2.2nF >> 1,980,000μm^2 (too big!!) >> 1,980,000μm^2 (too big!!) L = 2.25H L = 2.25H >> …. (too big for design kit to make!!) >> …. (too big for design kit to make!!)

9. 9 First Order Butterworth Filter Design R = 100K  C = 0.159nF

10. 10 Algorithm Detail Decimation (Sinc Filter, Downsample) Measure Peak Amplitude (Peak Input Indicator) Digital Output Digital Peak Indicator Analog Input Lowpass Filter Analog to Digital Conversion (Delta-Sigma Modulator) Digital

11. 11 Digital Design Updates Switch from Sinc3 to Sinc2 Filter Switch from Sinc3 to Sinc2 Filter Switch from 25 bits to 18 bits Switch from 25 bits to 18 bits

12. 12 Simulation of a 1 st order modulator with a 2 nd order Sinc filter

13. 13 Transistor count Total = 14,441 transistors 16-Bit Adder448 16-Bit Subtractor480 12-Bit Register216 16-Bit Register228 12-Bit Equality Function138 16-Bit Multiplexer96 Clock Divider334 2nd order Sinc Filter3296 PII Function2782 Decimator6412 Analog Op-Amps11

14. 14 Propagation Delay 16-Bit Adder2.856ns 16-Bit Subtractor2.916ns 12-Bit Register1.065ns 16-Bit Register1.065ns 12-Bit Equality Function270.5ps 16-Bit Multiplexer24.7ps Clock Divider241.5ps 2nd order Sinc Filter8.748ns PII Function2.950ns Decimator8.748ns

15. 15 Power Consumption 16-Bit Adder22.47W at 5.12MHz 16-Bit Subtractor28.54W at 5.12MHz 13.09W at 20KHz 12-Bit Register22.41W at 20KHz 16-Bit Register33.17W at 5.12MHz 29.88W at 20KHz 12-Bit Equality Function3.323W at 20KHz 16-Bit Multiplexer2.114W at 20KHz Clock Divider4.812W 2nd order Sinc Filter227.1W PII Function115.9W Decimator347.8W Digital

16. 16 Power Consumption FilterNegligible power consumption Modulator >> 2 op-amps >> power of 1 op-amp = 270μW 540μW Analog

17. 17Area Filter273.76μm^2 Op-Amps >>11 transistors 18.95μm^2 Modulator30,912μm^2 Analog Total = 31,205 μm^2

18. 18 Coming up next… Analog Analog fine-tune the modulator topology fine-tune the modulator topology Digital Digital finish schematic simulation/verification at the top-level, and beginning layout of basic modules such as the full adders and flip-flops finish schematic simulation/verification at the top-level, and beginning layout of basic modules such as the full adders and flip-flops

19. 19 Problems and Questions experiencing problems using the internally generated nyquist clock separately, but are still unable to get the entire top-level design to work properly experiencing problems using the internally generated nyquist clock separately, but are still unable to get the entire top-level design to work properly