1. 1 GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation 6: Component Layout & Floorplan March 6, 2006 Overall Project Objective: Design a low-power chip that navigates an aircraft to pre- determined waypoints.

2. 2 Status Design Proposal Design Proposal Architecture Proposal Architecture Proposal Size Estimates / Floorplan Size Estimates / Floorplan  Schematic Design Top-level wiring Top-level wiring Cell Analysis Cell Analysis Individual Schematics Simulated Individual Schematics Simulated Clock Speed Clock Speed Updated Floorplan Updated Floorplan Power Estimates at Targeted Clock Speeds Power Estimates at Targeted Clock Speeds  Top-level simulated  Critical Path Estimates  Layout Basic Gates Basic Gates Registers Registers SRAM Bit Cells SRAM Bit Cells  Everything Else  Simulations

3. 3 Design Decisions  No Combination of Heading & Waypoint Comparators  Register Optimization

4. 4 Why Didn’t We Merge Modules?  Power! 4096Hz Heading 8Hz Waypoint 2048Hz * * * * Heading+ Waypoint

5. 5 Clock v. Power Comparisons Clock Angle Calculator Static 1-Bit Register Dynamic 1-Bit Register 8Hz4.71nW1.19nW45.82nW 8Khz16.69nW12.32nW57.79nW 8Mhz10.89uW30.95nW539.4nW 200Mhz266.6uW282.5nW17.41uW

6. 6 Block Level System Diagram

7. 7 Inputs Blackbox Outputs

8. 8

9. 9 FSM Schematic Verification Clock Range SRAM Counter Inputs Outputs Input Mode SRAM Mode Control SRAM Modes 0=Read 1=Write 2=No Op 3=Reset Write No Op ReadReset {

10. 10 Power Consumption

11. 11 Cell Analysis Functional Component Recent Count Area (µm²) Power FSM2722,0001.02nW SRAM3,98817,000305.5uW Registers/Buffers Clock / Counter Logic Done Logic 6,2101,91254828,50010,5003,5009.8uW-- Speed Comparator Altitude Comparator Waypoint Comparator 2564123,6969001,90016,000902pW1.42nW225.4uW Heading Calculator Distance Calculator Speed Calculator Angle Calculator 3,4563,4281,6261,24615,50015,5007,0006,50015.59nW11.12nW5.82nW4.71nW Total27,050124,800540.7uW

12. 12 SRAM Bit Cells

13. 13 What’s Next… Here’s what’s on our agenda for next week…  Finish schematic top-level verification by Thursday  Critical Path Estimates  Component Layout

14. 14 Questions???