1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #13: Smart Cart 525 Stage XII: 20 April 2005 Short Final Presentation

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout DRC of functional blocks LVS of functional blocks Chip Level Layout Full chip LVS Simulations Schematic with loaded inputs/outputs ExtractedRC Full chip simulation (both parts verified separately)

3. Agenda For Final Presentation Title Slide Project Description (Bowei) Marketing (Bowei) Behavioral/Algorithmic Description (Syed) Design Process (Jenna) Floorplan Evolution (Jenna) Verification (Idong) Issues Encountered (Jonathan) Specifications (Jonathan) Layout (Jonathan) Conclusions (Bowei)

4. Project Description What the heck are we doing with this chip?

5. Marketing Why should you care about our product?

6. Behavioral/Algorithmic Description Diagram through the process (visio) Flow through the schematic/block diagram We’ll have some cool animation of some type

7. Design Process What the heck did we do from week 1 to the end of the semester? Encryption (cut down from 128 to 32 bits) Verilog  schematic  layout

8. Floorplan Evolution Show our very first floorplan and other “important” floorplans along the way culminating our last and final floorplan

9. Verification Use graphs/tables to show that all stages of the design process (behavioral/structural verilog, schematic, layout, post layout) produce the same correct outputs

10. Issues Encountered Crap that we had to deal with this semester

11. Specifications Pin specifications Part specifications (component transistors counts, area, density) of encryption, multiplier, adder, and sram Chip specifications (overall transistors counts, area, density)

12. Layout Layer masks (active, poly, metal1-metal4) Full chip layout Full chip layout with overlaid floorplan

13. Conclusions Our conclusions