1. Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 5: Feb. 18 th Component Layout Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

2. Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Floorplan & Structural Verilog Gate Level Design (done) Top Level Schematic Verification Component Layout Bit slices of components (done) Analog simulation of SRAM and ROM Layout of components (in progress) To be done Component Simulation Chip Layout & Simulation

3. Design Decisions / Goals Using NAND decoders for ROM and SRAM Registers with gated clocks instead of Latches 1 Mhz clock speed Fast enough to load SRAM and calculate pulse width for first engine rotation Slow enough to not waste extra power Main objective: low transistor count = low cost

4. Top Level Verification

5. Analog ROM Simulation

6. Analog SRAM Simulation

7. 12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]

8. Bit Slice Layout SRAM MUX

9. Bit Slice Layout Half AdderFull Adder

10. Component Layout Multiplier 12-bit 4:1 Mux

11. Floorplan Pin Distribution: 5 12-bit inputs 12-bit output 7-bit index input Clk, write, block, valid ---------------------- 83 I/O pins 8X10 SRAM Multiplier Comparator MUxMUx Control ROM 500µm 7X4 SRAM 400µm

12. Top Level Layout

13. Old Transistor Count Registers (5 12-bit, shift)2,568 SRAMS (1 8x10, 1 7x4)6,720 Comparator410 MUXs (2)696 Control Logic1,000 12-bit FP Multiplier3,096 Decoders1,000 TOTAL15,490

14. Updated Transistor Count Registers (7 12-bit, 2 3-bit, 1 5-bit)2,280 SRAMS (1 8x10, 1 7x4)7,776 Decoders (1 5:17, 1 5:28, 1 7:80)910 Comparator410 MUXs (1 4x1 12-bit, 1 2x1 12-bit, 1 2x1 7-bit, 1 2x1 5-bit, 1 2x1 4bit) 1,160 Control Logic (ROM)102 12-bit Fixed Point Multiplier3,096 Signal Buffering500 TOTAL16,234

15. Questions????