1. Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan March 1, 2006 Component Layout and Floorplan Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator Layout Count: 14,300

2. Agenda Status Design Decisions Verification & Simulation Review DFM & Layout Rules Critical Layouts Floorplan & Design Specs

3. Status Former C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Currently  Layout (14,300 of 34,710) Awaiting Extraction, LVS, post-layout simulation

4. Design Decisions Registers Re-designed –All registers based on n-pass DFF –Reduce size, power, complexity Reduction in instances of t-gates & inverters

5. DFF w/ Synchronous Load & CLR

6. Register Comparisons TypeTransistorsPower DFF1810µW HLFF2660µW

7. Verification Tested structural verilog against C code for correct result. Tested verilog schematic against structural verilog for matching signals Performed spectre analysis of key modules

9. DFM & ME The Rules –Everything is on a grid –Everything is mono-directional –All metal widths are the same –Contacts same width as metals

10. Pros Regular Layout Enforced Standardization More Accurate Resolution Contacts match metal widths

11. Example: Group Propagate

12. CONS Harder to “cut-corners” More time-involving Increased Area Decreased Speed More Metal Layers Learning Curve

13. Minimize Inverter Use DFM rules make inverters the more wasteful than any other gate No good way to make them, either waste area or avoid inverters

14. MUX’s Inefficient No routing through it BIG

15. 3 Bit Adder Block Completed Layouts:

16. 3 Bit Adder Block

17. SRAM Single Bus Cell Double Bus Cell

18. SRAM (R)

19. SRAM (M)

20. Updated Floorplan

21. Putting it All Together (Updated power calculations) ComponentTransistor CountAreaProp Delay Power Adders (4x)5856 (1464 each) 2700um 2 (675um 2 ea.) 1.44ns575uW FSM194100um 2 826ps46uW SRAM17736 (M=10458 R=7278) 8000um 2 735psW: 510uW R: 190uW Datapath w/o Adders 109245000um 2 3.3 mW Total3471015800um 2 500 MHz ~6.5mW

22. Thanks! Any Questions? (Beware the Cadence Ninja)