1. ADPCM Adaptive Differential Pulse Code Modulation
Team M4
Andrew Akindele
Edward Shim
James Lee
Anthony Xu
Project Objectives
Stage 6
Component Layout
(Corrected)
Design and implement an Adaptive DPCM
Manager : Joe Bakker
Date
March 3rd, 2003
Integrated Circuit Design Project

2. 18-525 Integrated Circuit Design Project
Project Status
Done
C and Verilog Coding
Schematics
Gate Level Layout
Functional Block Layout (98%)
Functional Block Simulations (98%)
Component Correction and Optimization
More Accurate Floorplanning
Next
Chip Wiring
Simulations and Verification
Integrated Circuit Design Project

3. 18-525 Integrated Circuit Design Project
New Design Decisions
Added Some Buffers
Registers
ROM tables
Multiplexers
Macro Blocks
Just schematics
Integrated Circuit Design Project

4. Carry Lookahead Adder (OLD)
Dim:
x 139.2
Transistors
814
Density
0.036 tr/um2
Integrated Circuit Design Project

5. Carry Lookahead Adder (OLD)
Tprop = 6.034ns
Integrated Circuit Design Project

6. Carry Lookahead Adder (NEW)
Dim:
143.9 x
Transistors
956
Density
0.066 tr/um2
Integrated Circuit Design Project

7. 16-bit Register (NEW) With Write Enabled
Dim: x 37.2 ; Transistors 328 ; Density tr/um2
Integrated Circuit Design Project

8. 16-bit Register (NEW) Without Write Enabled
Dim: 76.1 x ; Transistors 224 ; Density tr/um2
Integrated Circuit Design Project

9. 16-bit Register (write_en)
Trise = 0.35ns
Tfall = 0.19ns
Tprop = 1.05ns
FGOOD = 333MHz
Integrated Circuit Design Project

10. 8-bit Register (NEW) With Write Enabled
Dim: 65.3 x 37.2 ; Transistors 164 ; Density tr/um2
Integrated Circuit Design Project

11. 8-bit Register (NEW) Without Write Enabled
Dim: 38 x 35.4 ; Transistors 112 ; Density tr/um2
Integrated Circuit Design Project

12. 18-525 Integrated Circuit Design Project
ROMstep (OLD vs. NEW)
Dim:
x 74.1
Transistors
1,791
Density
0.138 tr/um2
Dim:
x 81.8
Transistors
1,855
Density
0.131 tr/um2
Integrated Circuit Design Project

13. 18-525 Integrated Circuit Design Project
ROMstep
Tprop = 2.74ns
Integrated Circuit Design Project

14. 18-525 Integrated Circuit Design Project
21mux-16bits (OLD vs. NEW)
Dim: x 8.6 ; Transistors 96 ; Density tr/um2
Dim: 99.9 x 16.3 ; Transistors 104 ; Density tr/um2
Integrated Circuit Design Project

15. 18-525 Integrated Circuit Design Project
21mux-8bits (OLD vs. NEW)
Dim: 78.9 x 8.6 ; Transistors 48 ; Density tr/um2
Dim: x 16.3 ; Transistors 52 ; Density tr/um2
Integrated Circuit Design Project

16. 18-525 Integrated Circuit Design Project
21mux-4bits (OLD vs. NEW)
Dim: 39.7 x 8.6 ; Transistors 24 ; Density tr/um2
Dim: x 8.6 ; Transistors 28 ; Density tr/um2
Integrated Circuit Design Project

17. 18-525 Integrated Circuit Design Project
FSM (NEW)
Dim: 61.3 x 39.6 ; Transistors 141 ; Density tr/um2
Integrated Circuit Design Project

18. 18-525 Integrated Circuit Design Project
Ripple Carry Adder
Tprop-LOW = 0.767ns
Integrated Circuit Design Project

19. 18-525 Integrated Circuit Design Project
Ripple Carry Adder
Tprop-HIGH = 3.415ns
Integrated Circuit Design Project

20. Component Simulations
New tprop high
Old tprop high
New tprop low
Old tprop low
ROMstep
2.74ns
4.09ns
2.72ns
2.56ns
CLA 16-bit
6.034ns
RCA 8-bit
3.415ns
0.54ns
0.77ns
1.01ns
FSM
FGOODnew = 333Mhz
FGOODold = 250Mhz
Clamp_index
1.76ns
1.61ns
1.64ns
1.84ns
Register
tprop high = 0.91ns
tprop low = 1.05ns
FMAX = 333Mhz
Integrated Circuit Design Project

21. 18-525 Integrated Circuit Design Project
Component Numbers
Component
New
Trans.
Old
New Dim.
Old Dim.
Density
C.L. Adder
956
814
143.9x100.2
162.3x139.2
0.066
Reg. 16-bits(w)
328
304
126.9x37.2
0.069
Reg. 16-bits
224
208
76.1x39.2
0.075
Reg. 8-bits (w)
164
156
65.3x37.2
0.068
Reg. 8-bits
112
100
38.0x35.4
0.083
ROMstep
1,855
1,791
172.9x81.8
172.9x74.1
0.131
Mux 16-bits
104 96
99.9x16.3
157.3x8.6
0.064
Mux 8-bits 52 48
51.6x16.3
78.9x8.6
0.062
Mux 4-bits 28 24
47.2x8.6
39.7x8.6
FSM
141
137
61.3x39.6
0.058
Integrated Circuit Design Project

22. 18-525 Integrated Circuit Design Project
Macro Blocks
Sub-mux
16bit subtractor
16bit – 2to1 mux
Diff-step
Sub-mux-inv
inverter
Add-mux
16bit adder
Integrated Circuit Design Project

23. Detailed Floorplan (v.1)
Dimensions:
500 x 480
Integrated Circuit Design Project

24. Detailed Floorplan (v.2)
Dimensions:
450 x 480
Integrated Circuit Design Project

25. 18-525 Integrated Circuit Design Project
Questions?
Integrated Circuit Design Project