Performed by: Ariel Wolf & Elad Bichman Instructor: Yuri Dolgin המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו”ח סיכום פרויקט סופי OCR Implementation on FPGA סמסטר חורף תשס"ג 1

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 OCR (Optical Character Recognition) systems are capable of recognizing optical images of text objects and convert them into their suitable ASCII code. Usually implemented by software, these programs consume a lot of resources due to their computational complexity. In this project we have developed an OCR hardware system which is based on a Neural Network paradigm, a concurrency mathematical model that can be efficiently implemented in hardware.

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 There are 4 Neural Nets implemented on the FPGA. For each image streamed into the chip, there are 6 iterations. On each one, all 4 nets work concurrently and represent different letters. After all nets have been simulated on the input, the output is chosen to be the letter which its representing net’s result is the highest. All the weights required for the neural nets calculation are written into 2 off chip SRAM memory modules, attached to the PCI card, on initialization. The weights are calibrated by a specific Matlab program that handles all the training phase.

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 4 Hardware  PCI development card 32 bit/33 Mhz from Nallatech  Xilinx Spartan II ® user FPGA – XC2S150  2 IDT Asynchronous SRAM (64K x 16 bit ) Software  Microsoft.NET framework  Nallatech software library.

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 SRAM I SRAM II OCR FPGA PCI FPGA 40 bit 32 bit 16 bit

FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 network1 network2 network3 network4 Max Logic D-FF MAX Input image 14x11 result