Presentation is loading. Please wait.

Presentation is loading. Please wait.

Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.

Similar presentations


Presentation on theme: "Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי."— Presentation transcript:

1 Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Network Interface Card using FPGA Spring 2003 1

2 Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 A regular Network Interface Card (NIC) contains only one chip to communicate with the network and the PCI bus. In this project we added a level of processing between the network controller and the PCI bus. This level is implemented by FPGA chip. This design enables manipulation over the received and transmitted frames by hardware, so the load of the software is reduced.

3 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The communication board connects to a PCI slot on the mother board. A PCI bridge converts the PCI bus to the simpler local bus protocol which is used to connect to the FPGA. All requests from the dedicated driver either refer to the inner PCI bridge registers or are passed for the FPGA. The FPGA then sorts the requests according to the action requested and carries out the right protocol against the desired communication path. It returns either a success signal or a failure signal.

4 Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Full control over the card via the driver. The Driver was developed using WinDriver. VHDL modules implements the above design on the FPGA chip.

5 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 FPGA PLXPLX MACMAC PHYPHY PCIPCI ETHERNETETHERNET - Data Flow - Control Signals

6 FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 PCIBRIDGEPCIBRIDGE MACMAC PHY CIFCIF GNR MCF TRN RCV ARB Shared bus


Download ppt "Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי."

Similar presentations


Ads by Google