1. Performed by: Asaf Gal Elad Ilan Instructor: Alex Zviagintsev המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Spike Sorting Algorithm Implemented on FPGA סמסטר חורף 2003 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 In this project a neuronal spike-sorting algorithm is implemented on chip, which will operate as part of a computer assisted system for neuronal spike sorting. Such a chip does the data processing “on site” saving the need to send huge amounts of raw data to a computer. The results will be compared to the results of a full PCA sort & detection algorithm.

3. Algorithm Description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Minimal PCA Algorithm with spike detection:  detection is part of the sorting problem!  Many spike-starting points are tried, relative to a certain threshold crossing.  The projection of each “guess” on the 1 st PC is checked to find maximum – the actual spike.  The actual spike is projected on the 2 PC’s and compared with PCA space separation lines. Specification Low frequency: ~100KHz input rate. Small H/W as possible Very low power consumption Low output rate as possible

4. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

5. Core Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6

6. Timing & State Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6