1. Performed by: Reshef Dahan & Yifat Manzor Instructor: Eran Segev המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט ( סופי ( Satellite image compressor controller פרויקט שנתי 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 This project is aimed to give an answer to the on-going increase of demand for high quality and high speed image processing, especially within the intelligence community. As the years go by, Hi-Tech devices like controllers and processors become more and more fast and efficient. Thus shifting the bottle neck of a data flow to the memory capacity. This situation has created a demand for parallel systems, that can handle a large amount of data in a very short time. This fact is emphasized when the data flow is installed on a satellite and the ability to transmit a large amount of data in short time is essential to the satellite’s mission. In this case the power consumption becomes an important factor as well. In this project we take advantage of a high speed controller capabilities to create a parallel system that is also power-efficient which utilizes JPEG2000 compressors, thus creating a very high speed and high quality image storing system.

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3  Raw data is received at high speed of 80MHz rate from the camera  Due to compressors capabilities, power consideration and other system requirements the data is split by the DIVIDER into 3 stripes and sent to 3 compressing units which include the ADV202 JPEG2000 compressors  The data is then compressed in these compression unit s. Due to the high speed of the divider, the compression is done parallelly in all 3 compression units.  The compressed data is then drawn by the MERGER where it is arranged into neat and well organized data packages. Each package is preceded by it’s own header. This header makes it easy and simple to decompress the data back into an image per demand.

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Xilinx evaluation board - VirtexIIpro FPGA component – 2VP30ff1152-6 JPEG2000 compressors – ADV202 Software Aldec Active-HDL ModelSim ; SimPlus Mentor HDL Designer Synthesis – Synplicity Sinplify ; XST P&R - Xilinx ISE C environment Simulation – Microsoft Visual Studio. 4

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 ADV202 Rocket I\O Xilinx ’ s development board – Virtex2Pro camera FPGA Memory

6. FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 DIVIDER Compression Unit MERGER Compression Unit Compression Unit Rocket I/O (raw data from camera) Compressed data (to memory)