1. Performed by:Fina Marganit Instructor: Ina Rivkin המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויק ט Subject: EXTENDED UART IP CORE Winter 2008 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 UART - Universal Asynchronous Receiver Transmitter In your PC, the UART is the key component of the serial communications port. Data is transferred within the computer in units of 1 to 8 bytes, with a separate wire for each bit within the byte (parallel form). The UART receives a byte and converts it to serial data and then sends out the data through a serial port,The UART can also converts incoming serial data from a serial port into parallel form (back into bytes).

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The UART is divided into three main sub-systems: The transmitter unit (TX) - is responsible for converting the parallel data into serial data and sending it out through a serial port The timing unit –is responsible for dividing the external clock to a transmitter unit’s clock and to a receiver unit’s clock,according to the Baud Rate,that is requested. The receiver unit (RX) – is responsible for receiving the serial data and converting it from a serial data into a parallel one.

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Xilinx’s Virtex II Pro platform design 4

5. 5 Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Software HDL Designer Snplify Pro I.S.E 4

6. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5