1. Performed by: Yevgeny Kliteynik Ofir Cohen Instructor: Yevgeny Fixman המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Nios Multi-Processor Ethernet Embedded System שנה : 2002 – 2003 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Embedded Systems role in the High-Tech world is growing. New embedded systems require a larger amount of flexibility, computation power and reliable I/O devices. This goal can be achieved by using Multi-Processor System with an explicit distribution of tasks. This way one CPU handles I/O tasks, and the other handles calculation tasks. Altera’s Nios embedded processor is a user-configurable, general-purpose RISC embedded processor. Gidel’s development board with an Altera FPGA is a suitable platform for combining System On Chip with peripheral devices. I/O Interface Common Memory Controller and Arbiter CPU 1 Extensive Calculation Tasks CPU 2 I/O Tasks

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The system that was build in this project achieves the following goals: Combining Ethernet card with embedded system on Gidel development PCI board. Building Multi-Processor SOC (System On Chip) that consists of two Nios processors with an explicit distribution of tasks:  CPU that handles I/O tasks through Ethernet connection.  CPU that handles extensive calculation tasks. Sharing a common external SDRAM by both Nios CPUs. Writing a software application that demonstrates the concurrent functionality of the system. Building a platform for rapid development of the embedded system on Gidel PCI card using Altera Nios technology.

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Proc20K - Gidel PCI development board with:  Altera FPGA chip – APEX EP20K Output voltage 0v – 2.5v Input voltage 0v – 5v  Four Micron SDRAM chips – total size 64MB  Internal clock – 50MHz, can be configured to 25MHz  Voltage supply – 5v, 3.3v and 2.5v Ethernet card – Crystal LAN CS8900A  Connection speed 10Mb/sec  Internal oscillator – 20MHz  Fed by voltage supply of 3.3v Ethernet card connector  Fed by voltage supply of 3.3v  Implementation – pin-to-pin wire-up Serial Port adaptive connector  Voltage converter – MAX232CPE  Fed by voltage supply of 5v  Conversion ranges: [-12v, 12v] – [0, 5] System clock rates  Nios CPU core – 25MHz  Micron SDRAM – 25MHz SW Application was written to demonstrate the parallel operation of the system. Nios CPUs roles in the application:  I/O CPU, where I/O device is Ethernet card  CPU for mathematical calculations. The application implements cracking Diffie-Helmman protocol of symmetrical encryption.

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Gidel PCI Card Apex FPGA SDRAM PLX PCI IF Adaptive Connector SDRAM Controller Nios CPU (Math) Germs Nios CPU (E-net) Germs Uart Selection Serial Port Connector Ethernet Card Serial IF E-net IF

6. FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 System Modules SDRAM Controller A v a l o n B u s BridgeBridge Nios CPU (Math) Uart 1 Ethernet Module Uart 2 Nios CPU (E-net) Germs 2Germs 1 Ethernet EF Serial IF SDRAM IF Uart Selection Logic