Performed by: Vyacheslav Yushin Igor Derzhavetz Instructor: Karina Odinaev המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט סופי Subject: Implementation of neuronetwork system on FPGA סמסטר חורף 2006 שנה 1

Abstract The major problem of CLA neuron-network system is low performance, making this principle hard and expensive in utilizing. The software implementation for CLA systems is extremely inefficient, because, only one operation can be performed per cycle in CPU and memory accesses is lowering performance even more. The FPGA implementation of CLA neuron network is much more efficient. The FPGA perform all network calculation in one cycle, and no memory access needed, because CLA networks are constants. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The internal CLA networks are implemented as drop-in module to ease the passing from one platform to another. CLA network build on the basis of the connectivity matrix received from the instructor. In current project the envelope or system interface was USB – FIFO adapter, because of this fact, the simple RISC (reduced instruction set computer) was developed to work with the CLA networks and input devices. Also was developed special software module for the data transmission from the PC to the FPGA board through the USB FIFO adapter.

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 XUPV2PXUPV2P FPGA board. XUPV2P DLP-USB245M USB Adapter PC with USB port. C++ class for flexible work with USB adapter VS6 was used as development platform USB adapter DLL and driver

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 USB control RISC executor Neuro Network Debug block Pre-processor USB control RISC exe PRE-PROCESSOR Neuronetwork to external pins