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Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony Cooperated with: Physics Adaptive Optics Lab המעבדה למערכות ספרתיות מהירות High speed.

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Presentation on theme: "Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony Cooperated with: Physics Adaptive Optics Lab המעבדה למערכות ספרתיות מהירות High speed."— Presentation transcript:

1 Performed by: Koren Erez & Turgeman Tomer Instructor: Orbach Mony Cooperated with: Physics Adaptive Optics Lab המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Subject: AMC – Adaptive Mirror Controller 2006-2007 1

2 Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 The project is a collaboration between the Physics Adaptive Optics Lab and HS DSL. Developing a system that controls adaptive mirrors, by changing the voltage of their capacitors (up to 124 capacitors). The system will eventually be integrated into an optical device that present the image of the retina (the back of the eye). During this process the device will also fix the distortion of the picture that reflected by the cornea.

3 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 AMC MMC USB Adaptive Mirror D/A FPGA USB Interface Amp. 8 Bit 12 Bit

4 Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 FPGA – Altera Cyclone EP1C3T144C8 USB module - DLP-USB245M D/A – Analog Devices quad voltage output AD5334 High Voltage amplifiers – Supertex HV257 C++ driver based on the DLP-USB API

5 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 DLP (USB) Cyclone FPGA Computer Adaptive Mirror HVAmp Bus Exchange Relay Transceiver Quad Voltage Output D/A Transceiver Switches Latch Power Up/Down Unit HVAmp Power Supply CLKEPCSResetComparator '1' HVAmp

6 FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 State Machine ROM Asinc to Sinc System Power Down DLP, FPGA Power Up HVAmp Power Up MAIN Self test HVAmp Power Down DLP ready! HVAmps are powered on OK/Error Massage RUN Byte! All capacitors were charged/ WDTR! Shutdown Byte! Power off AMC + USB cable disconnection! Power on AMC + USB cable connection! RUN Self Test Byte! Status Byte! DLP to PC Transmi t EOT EOT = End Of Transmission WDTR = Watch Dog Timer Reset DLP = USB Module HVAmp = High Voltage Amplifier The Control Bytes are marks in green


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