Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #7: Smart Cart 525 Stage VII: 28 Feb Functional Block Layout and Floorplan
Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout (still working on encryption) DRC of functional blocks LVS of functional blocks Simulations
Design Decisions Modification to floorplan Some components smaller than expected Moved 32-bit mux/buffer/reg/buffer from encryption block to main block; needed to make encryption skinnier and main fatter Moved SRAM to top, adder to bottom, and registers on top of SRAM Using row decoder of SRAM as routing channel for 20-bit input and 14-bit output bus
Design Decisions Decided on modified master-slave DFF for input/output registers Don’t have to gate clk this way Plan to use regular master-slave for other registers in the design
Updated Transistor Count OldNew Encryption13,054 Multiplier Adder SRAM2276 Logic Registers (inputs/outputs, counters) Total22,43420,856
Updated Floorplan Estimated Area:Old (μm 2 )New (μm 2 ) Encryption68,352 Multiplier12, Adder SRAM963910,695 Logic/Wiring10,72114,655 Registers (inputs/outputs, counters) Total111,744110,968 Estimated density: ( transistors/μm 2 ).2.19
Old Floorplan: Entire Design
New Floorplan: Entire Design v SRAM Input Registers Adder v Multiplier
Floorplan: Fitting everything together Registers A closer look
Floorplan: Global wiring done on individual blocks
Floorplan: Global wiring end result
Layout: Encryption (Small ROM)
Layout: Encryption (Mix Column)
Layout: Encryption (SBOX)
Layout: Multiplier
Layout: Carry-Select Adder
Layout: Register (Old)
Layout: Register (New) To be used for input/output registers
Layout: Register To be used elsewhere in the design (counters, etc.)
Problems & Questions Simulations for Adder/Multiplier: ran, but weren’t good XOR implementation of FA led to some signal strength problems in simulations Need to add buffers, which will possibly fill up some extra space left by initial layout Wiring in encryption block