1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #2: Smart Cart 525 Stage II: 24 Jan. 2005 Architecture Proposal

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated  Gate-level implementation  Schematic Design  Floorplanning  Layout  Simulations

3. Our chip will: Take in an 8-bit product ID from RFID receiver to find product price from a lookup table Keep a running total price for items to be purchased (allows for addition/removal of items from cart) Calculate subtotal, tax, total, and take store coupons into account Use Rijndael encryption to securely transmit customers’ 32-bit store card information to store’s central computer Update price list between transactions if needed About the Smart Cart 525

4. What exactly is RFID? RFID tag: Antenna attached to a microchip which contains a unique 32->2048 bit ID code. Tag listens for radio query and responds with its ID information, no power needed. Versatility of RFID technology makes this marketable for other purposes as well  Applications: aircraft manufacturing, consumer electronics, baggage tracking in airports “Virtually every company on Earth will be required to use RFID in one way or another to remain competitive in the global market.”

5. Why use this chip? Quicker shopping, wait-free Secure transactions with AES encryption Low-cost (counterexample: IBM and Cuesol’s “Shopping Buddy”) Low power consumption Easy to maintain, update prices when being recharged at base stations.

6. Alternative Projects Neural chip - Implement a chip in the motor cortex of the brain to control motor movements of the prosthetic limbs. Total workout machine - Optimize workout by keeping track of bodily functions. JPEG filtering Blood sugar monitor

7. Design Flow: Week 1

8. Design Flow: Week 2

9. Multiplier, adder: floating point vs. non-floating point  Decided on non-floating point (multiplier will be big enough already—tentatively 14x5) Encryption: AES vs. DES (and how many bits?)  Decided on 32-bit AES since AES is the new standard  Anything smaller than 32 bits not doable with Rijndael algorithm Speed vs. power, pipelining  Low power, low speed to save battery power. No pipelining. Bit width of I/O pins  RFID code (simplified to 8-bit) etc to make our project manageable Design Decisions: Week 1

10. Design Decisions: Week 2 Divided design into four different blocks instead of one block  Hoping to disable blocks not being used for current operation to save power (if we can figure out how to implement this) Multiplier: got bigger  14 x 7; ran into a problem with calculating tax (e.g. instead of multiplying by.06 for 6%, now multiplying by 1.06 to arrive at total without having to add the tax to subtotal Memory types  Price lookup table  SRAM (can be updated)  Coupon lookup table  ROM (hardcoded values)

11. Encryption  Figured out the 2x2 matrix for the MixColumn function Figured out the multiplication by the matrix using XORs and ANDS instead of using two more lookup tables to do the Galois Field Multiplication.  Key Expansion process Decided to generate the new key at each cycle rather than expanding it at once and storing all 44bytes. Design Decisions: Week 2

12. Problems & Questions: Week 1 Unsure about complexity of certain blocks, which held us back from deciding on final specifications Update: have final specifications Having trouble finding Verilog code, but making some progress Update: found Verilog for Rijndael and modified for 32-bit Rest of modules coded from scratch Encryption: too many algorithms out there, had to narrow down and simplify (reduce number of bits) to fit the scope of this course Update: decided on algorithm and modified to suit our project

13. Problems & Questions: Week 2 How to actually disable certain blocks to save power  Is this even possible?  Demux? When to start the encryption process and how to control the total amount customer will pay  When encryption starts, we don’t want the total amount or card number to change. We assume they won’t but if we had some noise that caused the adder or multiplier to change the total, that would be very bad. Behavioral simulation not complete  Might need to rethink the datapath to better clarify what controls what

14. Verilog Testbenches & Simulations 128-bit Encryption Data = 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Key = 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Output/Cipher Text = 0A 94 0B B5 41 6E F0 45 F1 C3 94 58 C6 53 EA 5A 128-bit Rijndael Verilog code found on OpenCores.org works. The data and key used presented the correct cipher text.

15. Verilog Testbenches & Simulations main test(Credit_Card, Lookup_codes, PurchaseOrRemove, Tax, DoUpdate, Operation_codes, New_Price, clk, finalTotal, Encrypted_Datareg); initial begin $monitor($time,,"clk=%b, finalTotal=%d, Encrypted_Datareg=%b",clk, finalTotal, Encrypted_Datareg); Credit_Card = 32'h0D8A231E; Lookup_codes = 4'b0; Tax = 3'b011; DoUpdate = 1'b1; clk = 1'b0; //WRITE PRICES INTO LOOKUP TABLES //DoUpdate asserted high #5; Lookup_codes = 4'b0000; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b0001; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b0010; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b0011; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b1000; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b1010; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b1000; New_Price = 10'b0010011101; #10; Lookup_codes = 4'b1010; New_Price = 10'b0010011101; #10; //PERFORM ADD OPERATIONS //DoUpdate asserted low DoUpdate = 1'b0; PurchaseOrRemove = 1'b1; Lookup_codes = 4'b1000; #10 Lookup_codes = 4'b1010; #10 Lookup_codes = 4'b0000; //PERFORM REMOVE OPERATIONS //DoUpdate asserted low #10 PurchaseOrRemove = 1'b0; Lookup_codes = 4'b1010; //CHECKOUT //DoUpdate asserted low, when done, DoUpdate can be asserted high #200$finish; end always #5 clk = ~clk; endmodule

16. Rough Transistor Count Encryption~7000 Multiplier~4000 Logic~2000 Adder~500 SRAM~5120 Registers (inputs/outputs)~1200 Total~19,820