1. E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon, Nov 10 Functional Layout Blocks Floor plan + global connect update Secure Electronic Voting Terminal

2. Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX 01 01 01 16 bit Add/Sub 01 8 bit MUX 16bi t REG 8-bit REG COMMS Register Shift Registe r In Shift Registe r Out constant init

3. COMMS Layout Complete DRC + LVS Complete Next time: Global wiring optimization Extracted Simulation

4. COMMS Full Schematic Components FF 8 bit (2) FF_C 16 bit (1) XOR 8 bit (4) Inv (1) FA 8bit (4) FA 16 bit (1) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4)

5. COMMS Full Layout 82 by 80

6. COMMS Full Layout 82 by 80

7. FSM Machine Initialization FSM is working User ID FSM is not working Selection FSM is working Confirmation FSM is not working Next time: Finish debugging minimum hold time bugs Clean up Layout

8. FSM Bugs Most FSM bugs came from not meeting the minimum hold time on the edge sampled Flip Flops This caused glitches which activated states early

9. FSM Bugs 2 of the FSMs have been debugged and simulated in the analog environment The analog simulations were not exhaustive. The other two FSMs still have an early triggering problem in their address counters

10. FSM Floorplan

12. (not complete or LVSing)

13. SRAM Row decoders: Complete and LVSing SRAM layout: Complete and LVSing Next time: ?

14. SRAM and Decoder Layout

15. SRAM TriState Buffer

16. FLOORPLAN Updated floorplan based on functional blocks

17. Old Floorplan ●The aspect ratio 2:1 ●Doubled size in COMMS Block ●The interconnects travel heavily over the FSM ●These are mostly 1 bit enable signals and some are address lines ●The address lines and data bus are buffered

18. Encryption Key SRAM (4 byte) 2bit Address 8bit Data Machine Initialization FSM 1bit Activate next Data Bus COMMS 1bit Data Ready 8bit Data 1bit Message Message ROM 8bit Data 4-bit Data bus control Machine Initialization FSM

19. User ID SRAM (8 byte) 3bit Address 8bit Data User ID FSM 1bit Activate next Data Bus COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this 1bit Reactivate this Display 8bit Data 7-bit Data bus control User Input 1bit Yes Signal 1bit No Signal User ID FSM

20. Choice SRAM (4 byte) 2bit Address 8bit Data User Input 1bit Next Page Signal Selection FSM 1bit Activate next Data Bus 8bit Data COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this 1bit Reactivate this Display 8bit Data 6-bit Data bus control 1bit Previous Page Signal Selection Counter 8bit Data 3bit Count Selection FSM

21. User Input 1bit Yes Signal Confirmation FSM 1bit Reactivate Selection Data Bus COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this Display 8bit Data 8-bit Data bus control 1bit No Signal 1bit Reactivate User ID User ID SRAM (8 byte) 8bit Data Write-in SRAM (64 byte) 8bit Data Choice SRAM (4 byte) 8bit Data 3bit Address 2bit Address 6bit Address 1bit Reset TX_Check 1bit TX_good Confirmation FSM

22. New Floorplan

23. ●147 by 132 ●The aspect ratio around 1:1 ●Increased size in COMMS Block ●FSM connects to message ROM, selection counter, tx_check directly ●FSM connects to SRAMS via data bus ●The address lines and data bus are buffered as seen with SRAM tri-state buffers ●COMMS only has 4 data_ready bits connected to FSM block

24. TODO: For Wednesday: Clean up and optimize functional layouts Functional extracted simulations For Monday:Complete smaller support logic blocks Complete Global interconnects Updated floor plan LVS & Extracted Simulation Whole Chip