1. Noise Canceling in 1-D Data: Presentation #10 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Mar 28 rd, 2005 Chip Level Layout 2 Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (93%) –Spice simulation (85%)

3. Design Decisions Redesigned the bottom fpAdder to better fit the new floorplan. Changed the wiring of the inputs and outputs of the toplevel registers and muxes.

4. Previous Floorplan

5. New and Improved Floorplan

6. Layer Masks - Poly

7. Layer Masks - Metal 1

8. Layer Masks – Metal 2

9. Layer Masks – Metal 3

10. Layer Masks – Metal 4

11. The Chip Dimension –Width = 377.19µ –Height = 303.3450µ Area = 114418.701µ² Transistor count = 25859 Density = 0.226 trans/µ² Aspect ratio = 1: 1.24

12. Floating Point Multiplier

13. 10-bit Wallace Tree Multiplier 20 bit output 2 10-bit inputs

14. Side components of the Multipliers Center Side Inputs Output

15. fpMult: Simulation Results (Extracted RC) Bits 8-15

16. Simulation Results (Schematics with Load Caps) Bits 8-15

17. Floating Point Adder

18. fpAdder Components

19. AlignShift: Simulation Results (ExtractedRC)

20. Registers 2 types of registers

21. 16 bit Register: Simulation Results (ExtractedRC)

22. 16 bit Register: Simulation Results (Schematic)

23. 16-bit 2-1 Mux

24. Simulation Results (ExtractedRC)

25. Simulation Results (Schematics with Load)

26. ROM

27. Simulation Results (Schematics with Load)

28. ROM Analysis Rise Time = 672.21 ps Fall Time = 620.4 ps

29. Questions?