Design Technologies Custom Std Cell Performance Gate Array FPGA Cost

Views / Abstractions / Hierarchies Structural Behavioral device Circuit Logic Architectural Physical D.Gajski, Silicon Compilation, Addison Wesley, 1988

N-Channel Enhancement mode MOS FET Four Terminal Device - substrate bias The “self aligned gate” - key to CMOS

The MOS Transistor Digital Integrated Circuits © Prentice Hall 1995 Introduction

MOS transistors Types and Symbols Digital Integrated Circuits © Prentice Hall 1995 Introduction D D G G S S NMOS Enhancement NMOS Depletion D D G G B S S NMOS with PMOS Enhancement Bulk Contact

The Basic Idea… Voltage on the Gate controls the current through the source/drain path N-Channel - N-Switches are ON when the Gate is HIGH and OFF when the Gate is LOW P-Channel - P-Switches are OFF when the Gate is HIGH and ON when the Gate is LOW (ON == Circuit between Source and Drain)

Transistors as Switches N Switch G S D 1 Passes “good zeros” P Switch G S D 1 Passes “good ones”

….The Rest of the Story... Put them in series - both must be on to complete the circuit Put them in parallel - either can be on to complete the circuit Generate all sorts of Switching Functions NOT the same as Boolean Functions.... Its RELAY logic - pin ball machines

Series Parallel Structures D 1 G S D D 1 1 G G D S S 1 G S N Channel: on=closed when gate is high

NMOS Transistors in Series/Parallel Connection Digital Integrated Circuits © Prentice Hall 1995 Introduction Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

Series Parallel Structures(2) D G S D D G G D S S G S P Channel: on=closed when gate is low

PMOS Transistors in Series/Parallel Connection Digital Integrated Circuits © Prentice Hall 1995 Introduction

Series Parallel Structures (3) N Switch G S D S 1 Passes “good zeros” G S D Passes “good ones” S’ 1 P Switch Open Circuit, High Z Bi-directional Switch

From Switches to Boolean Functions... Use the Switching Functions to provide paths to Vdd or GND Vdd is the source of all Truth (Vdd = = 1) GND is the source of all Falsehood (GND == 0) P-channel N-channel 1 1

The Inverter True to False / False to True Converter 1/0 0/1

…That’s it! This is Non-Trivial: it defines the basis for the logic abstraction which is essential for all Boolean functions. Provide a path to VDD for 1 Provide a path to GND for 0 For complex functions - provide complex paths

Four Views Logic Transistor Layout Physical

Cross-Section of CMOS Technology Digital Integrated Circuits © Prentice Hall 1995 Introduction

Magic Layout of Inverter

Magic “Palette” of Layers

Modern Interconnect

Chain of Inverters A B C D E Feedback loop

Which is which? A B C D E

CMOS logic structures Static (logic) structures Complementary structures Pass structures Pseudo-NMOS structures Dynamic (logic) structures precharged latched combinations Memory structures static quasi-static dynamic I/O structures

Complementary Structures Big -- 2 x N transistors for N inputs Use the “dual” for N and P chains Can/should be sized for maximum speed/minimum power-area Can use well known circuit minimization techniques Fast Low static power dissipation Possibly high dynamic power dissipation

Static CMOS Circuit Digital Integrated Circuits © Prentice Hall 1995 Introduction At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Static CMOS Digital Integrated Circuits © Prentice Hall 1995 Introduction

Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits © Prentice Hall 1995 Introduction

Example Gate: NAND Digital Integrated Circuits © Prentice Hall 1995 Introduction

Example Gate: NOR Digital Integrated Circuits © Prentice Hall 1995 Introduction