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Field-Effect Transistors 1.Understand MOSFET operation. 2. Understand the basic operation of CMOS logic gates. 3. Make use of p-fet and n-fet for logic gate implementation

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NMOS AND PMOS TRANSISTORS

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The MOS Transistor

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Cross-Section of CMOS Technology

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MOS transistors Types and Symbols D S G NMOS Enhancement G D S PMOSEnhancement

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NMOS

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Threshold Voltage: Concept

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PMOS

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Mode of Operation Cut off Liner Saturation

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Operation in the Cutoff Region

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Operation in the Linear Region

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Operation in the Saturation

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Transistor in Saturation

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MOSFET Summary

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CMOS Inverter

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MOS transistors logic input D S G NMOS Enhancement G D S PMOSEnhancement G =‘1’ then turn on the n-fet as Vgs > V threshold G = ‘0’ then turn on the p-fet as Vgs is negative as Vs > Vg

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CMOS NAND Gate

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CMOS NOR Gate

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The Ideal Gate

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Delay Definitions

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CMOS INVERTER

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The CMOS Inverter: A First Glance

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CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching

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Voltage Transfer Characteristic

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CMOS Inverter VTC

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Simulated VTC

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Where Does Power Go in CMOS?

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Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

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CMOS Logic Implementation A CMOS logic gate consists of p-tree for pull-up n-tree for pull-down.

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CMOS Logic Implementation Duality f = A+B’C if A = ‘1’, or B=‘0’ and C=‘1’, then f = ‘1’ if the logic function is in the form as f, then use Direct Implementation, for the P-tree implementation and logic function series connection so the term B`C is in series or logic function parallel connection so A, B`C is in parallel use complement of the input signals That is, A`, B and C` are used as inputs

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CMOS Logic Implementation f = A+B’C A = ‘1’ A`= ‘0’, P1 on B’= ‘1’ B = ‘0’ P2 on C = ‘1’ C`= ‘0’, P3 on either P1 on or P2 and P3 are on then f = ‘1’ Since ‘0’ is need to turn on the use A`, B and C` as the inputs to the P- tree, instead of the original input variables. Both p-tree and n-tree have the same set of inputs.

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CMOS Gate Implementation Once P-tree is designed, use duality for the N- tree Duality Series connection in P – tree parallel for N- tree Parallel connection in P-tree series for N-tree f = A+B’C if A = ‘1’, A`=‘0’, B’=‘1, B=‘0’ and C=‘1’, C`=‘0’, then f = ‘1’ pull up the output through the p-tree net if A = ‘0’, A`=‘1’, B’=‘0’, B=‘1’ and C=‘0’, C`=‘1’, then f = ‘0’ pull down the output through n-tree net

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CMOS Gate Implementation f = A+B’C A = ‘1’, A`=‘0’, P1 turn on or B’=‘1, B=‘0’, P2 turn on and C=‘1’, C`=‘0’, P3 turn on then f = ‘1’ pull up the output through the p-tree net through P1 or P2 and P3 if A = ‘0’, A`=‘1’, N1 turn on B’=‘0’, B=‘1’, N2 turn on or C=‘0’, C`=‘1’, N3 turn on then f = ‘0’ pull down the output through n-tree net through N1 and N2, or N1 and N3

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CMOS Gate Implementation If f is in this form, there are two ways to implement the logic gate for the logic function. 1.expand the logic function through de Morgan rule and direct implementation on the expanded function. f = (A+B`C)` = A`(B`C)`= A`(B``+C`) = A`(B+C`) Implement the logic gate with the previous method, the input signals are A, B` and C

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CMOS Gate Implementation Use duality to complete design for the n-tree

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CMOS Gate Implementation 2. Take then, g = A+B`C Use g to define the n-tree configuration. If g is true f = ‘0’ Same implementation rule apply, and logic function series connection so the term B`C is in series or logic function parallel connection, and input variables remain un-change A = ‘1’, g is true, N1 on B`= ‘1’, and C = ‘1’, g is true N2 and N3 are on

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CMOS Gate Implementation Use the duality to complete design for the p-tree.

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Comparison of Design Method f = (A+B`C)`, f =g`, g = A+B`C Use g to define the circuit configuration for the N-tree, and the input variables are those of the logic function, g; that is, A, B` and C By de Morgan rule on f, f = A`(B+C`), and use the expended form to define the circuit configuration for the P-tree, and the input variables are the complementary of the variables of the expended form. As f = A`(B+C`), the input variables are A`, B, and C`, the complementary of these signals are A, B` and C. Comparing the two approach, there is conflict between the two as the input variables are the same as A, B` and C. And the circuit configuration of P-tree and N-tree are in fact observe the de Morgan rule or duality.

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CMOS Gate Implementation It has to remind that the p-tree has to be connected to Vdd for pull-up the output and the n-tree has to be connected to GND for pull-down the output. It cannot use n-tree for the pull-up and p-tree for the pull-down as the full-swing property will not be maintained. i. e. logic ‘0’ ≠ zero volt logic ‘1’ ≠ Vdd volts

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