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**Lecture #24 Gates to circuits**

10/27/2004 EE 42 fall 2004 lecture 24

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**Topics Today: Implementing gates with MOS transistors Gate delays**

Glitches 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS and complementary logic**

Complementary PMOS and NMOS switches in parallel or in series with complementary logic to form high speed, low power logic PMOS devices turn on with low voltages, so we use them in the pull up circuit for a gate NMOS devices turn on with high voltages, so we use them in the pull down circuit for a gate 10/27/2004 EE 42 fall 2004 lecture 24

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**Pull up/Pull down +V Output**

Using CMOS, which has both NMOS and PMOS transistors, we can build gates which turn on a connection to +V when the output is supposed to be high, and another connection to ground when the output is supposed to be low. +V A B C (PMOS) Output (NMOS) 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS NOR VDD A B 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS NOR IF both A and B are low, then both pull up transistors are on**

VDD A B A+B And the output Goes high IF neither A or B are high then both of the pull down transistors are off 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS NOR IF either A and B are low, then at least one of the pull up transistors is off VDD A B A+B And the output goes low IF either A or B are high then at least one of the pull down transistors is on 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS NAND VDD A AB B 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS NAND VDD A B C 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS logic transitions**

If we look at CMOS with static inputs, it will pull up high logic levels all the way to the supply Low logic levels are pulled all the way down to ground. We will now look at the behavior of the circuits as they are switching, which will determine the performance of the logic 10/27/2004 EE 42 fall 2004 lecture 24

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**NMOS current vs. Voltage**

(Drain) current saturation values State 1 or VIN = 1V VOUT(V) 3 VDD =5 IOUT(mA) 20 60 100 State 3 or VIN = 3V State 5 or VIN = 5V The maximum voltage is VDD VOUT-SAT-D Current is flat (saturated) beyond VOUT-SAT-D Current is zero until VIN is larger than VTD 10/27/2004 EE 42 fall 2004 lecture 24

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**PMOS current vs. Voltage**

(Drain) current saturation values IOUT(mA) 20 60 100 State 5 or VIN = 5V Current is flat (saturated) below VOUT-SAT-D State 3 or VIN = 3V Current is zero until VIN is below VTD 3 VOUT-SAT-D VDD =5 VOUT(V) 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS Inverter Since CMOS uses one or more PMOS devices to pull up, and one or more NMOS devices to pull down, we can get most of the dynamics from an inverter. 10/27/2004 EE 42 fall 2004 lecture 24

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CMOS inverter VDD 10/27/2004 EE 42 fall 2004 lecture 24

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Since +V is the sum of the voltage across the NMOS device and the PMOS device, we can draw a composite IV plot for the two devices, showing the current which is available from each of the two devices. On the next slide, notice that when one device is turned on, and able to provide a lot of current, the other device is off 10/27/2004 EE 42 fall 2004 lecture 24

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**Composite IOUT vs. VOUT for CMOS**

PU current is flat (saturated) below VDD - VOUT-SAT-D VOUT(V) 3 IOUT(mA) 20 60 100 State 3 or VIN = 3V VOUT-SAT-D Pull-Up PMOS IOUT-SAT-U Pull-Down NMOS IOUT-SAT-D VDD =5 The maximum voltage is VDD PD current is flat (saturated) beyond VOUT-SAT-D Solution 10/27/2004 EE 42 fall 2004 lecture 24

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**Output Propagation Delay High to Low**

VOUT(V) 3 5 IOUT(mA) 20 60 100 VIN = 5V IOUT-SAT-D = 100 mA VOUT(0) = 5V COUT = 50 fF IOUT-SAT-D = 100 mA When VOUT > VOUT-SAT-D the available current is IOUT-SAT-D For this circuit when VOUT > VOUT-SAT-D the available current is constant at IOUT-SAT-D and the capacitor discharges. 10/27/2004 EE 42 fall 2004 lecture 24

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**Output Propagation Delay High to Low (Cont.)**

The propagation delay is thus 10/27/2004 EE 42 fall 2004 lecture 24

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**RD = ¾ VDD/ISAT has a Physical Interpretation**

VOUT(V) 3 5 IOUT(mA) 20 60 100 VIN = 5V IOUT-SAT-D = 100 mA VOUT(0) = 5V COUT = 50 fF IOUT-SAT-D = 100 mA ¾ VDD is the average value of VOUT Approximate the NMOS device curve by a straight line from (0,0) to (IOUT-SAT-D, ¾ VDD ). Interpret the straight line as a resistor with slope = 1/R = ¾ VDD/ISAT 10/27/2004 EE 42 fall 2004 lecture 24

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**Switched Equivalent Resistance Values**

The resistor values depend on the properties of silicon, geometrical layout, design style and technology node. n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type. The resistance is inversely proportion to the gate width/length in the geometrical layout. Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size. The current per unit width of the gate increases nearly inversely with the gate width. 10/27/2004 EE 42 fall 2004 lecture 24

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**Inverter Propagation Delay**

Discharge (pull-down) VOUT VDD VIN = Vdd COUT = 50fF VOUT VDD VIN = Vdd RD COUT = 50fF Dt = 0.69RDCOUT = 0.69(10kW)(50fF) = 345 ps Discharge (pull-up) Dt = 0.69RUCOUT = 0.69(10kW)(50fF) = 345 ps 10/27/2004 EE 42 fall 2004 lecture 24

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**Example using resistor model**

Using the resistor model, we can calculate the approximate rise and fall times for more complex gates, such as 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS Logic Gate NMOS and PMOS use the same set of input signals VDD**

B C VDD VOUT PMOS only in pull-up PMOS conducts when input is low PMOS do not conduct when A +(BC) NMOS only in pull-down NMOS conduct when input is high. NMOS conduct for A + (BC) Logic is Complementary and produces Vout = A + (BC) 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS Logic Gate: Example Inputs**

B C VDD VOUT A = 0 B = 0 C = 0 PMOS all conduct Output is High = VDD NMOS do not conduct Logic is Complementary and produces Vout = 1 10/27/2004 EE 42 fall 2004 lecture 24

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**CMOS Logic Gate: Example Inputs**

B C VDD VOUT A = 0 B = 1 C = 1 PMOS A conducts; B and C Open Output is High = 0 NMOS B and C conduct; A open Logic is Complementary and produces Vout = 0 10/27/2004 EE 42 fall 2004 lecture 24

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**Switched Equivalent Resistance Network**

B C VDD VOUT RU RD A B C VDD VOUT Switches close when input is low. Switches close when input is high. 10/27/2004 EE 42 fall 2004 lecture 24

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