1. Introduction to VLSI Design
Instructor: Steven P. Levitan
TA: Jeremiah Cessna
Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey
Lab Notes: at Copycat

2. Digital Integrated Circuits A Design Perspective
Jan M. Rabaey

3. Course Outline (approximate)
Introduction and Motivation
The VLSI Design Process
Details of the MOS Transistor
Device Fabrication
Design Rules
CMOS circuits
VLSI Structures
System Timing
Real Circuits and Performance

4. Reference Books
Principles of CMOS VLSI Design: Neil Weste and Kamran Eshraghian
CMOS: Baker, Li, Boyce
Application Specific Integrated Circuits: Smith
The Design and Analysis of VLSI
Circuits: Lance Glasser and Daniel Dobberpuhl
Introduction to VLSI Systems: Carver Mead & Lynn Conway
NewsGroups: comp.lsi, comp.lsi.cad

5. Software Magic Spice Irsim Unix Based Interactive Design Rule Checking
Circuit Extraction
Supported Technology files
Spice
Well known and disliked
Spice 3 allows user models
Good support/documentation
Interface with Magic extraction
Irsim
Switch / Switched - Resistor level
Fast functional validation
Good interface with Magic

6. The First Computer Digital Integrated Circuits © Prentice Hall 1995
Introduction

7. ENIAC - The first electronic computer (1946)
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

8. Evolution in Complexity
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

9. What is “CMOS VLSI”?
MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)
Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate. We call this “poly” or just “red stuff” to distinguish it from the body of the chip, the substrate, which is a single crystal of silicon.
We do use metal (aluminum) for interconnection wires on the surface of the chip.

10. CMOS:Complementary MOS
Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs).
Field Effect- NO current from the controlling electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
N/P Channel - doping of the substrate for increased carriers (electrons or holes)

11. N-Channel Enhancement mode MOS FET
Four Terminal Device - substrate bias
The “self aligned gate” - key to CMOS

12. VLSI:Very Large Scale Integration
Integration: Integrated Circuits
multiple devices on one substrate
How large is Very Large?
SSI (small scale integration)
7400 series, transistors
MSI (medium scale)
74000 series
LSI 1,000-10,000 transistors
VLSI > 10,000 transistors
ULSI/SLSI (some disagreement)

13. Intel 4004 Micro-Processor
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

14. Evolution in Transistor Count
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

15. Scale Example Consider a chip size of 20mm X 20mm
Consider a transistor size of 2um X 2um
With area for wires, etc.
1x108 transistors / chip
Or - plot at 1 transistor : 1 mm
1 chip : 20 meter x 20 meter plot

16. Intel Pentium (II) microprocessor
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

17. VLSI Design
But the real issue is that VLSI is about designing systems on chips.
The designs are complex, and we need to use structured design techniques and sophisticated design tools to manage the complexity of the design.
We also accept the fact that any technology we learn the details of will be out of date soon.
We are trying to develop and use techniques that will transcend the technology, but still respect it.

18. The Process of VLSI Design:
Consists of many different representations/Abstractions of the system (chip) that is being designed.
System Level Design
Architecture / Algorithm Level Design
Digital System Level Design
Logical Level Design
Electrical Level Design
Layout Level Design
Semiconductor Level Design (possibly more)
Each abstraction/view is itself a Design Hierarchy of refinements which decompose the design.

19. Design Abstraction Levels
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

20. Help from Computer Aided Design tools
Editors
Simulators
Libraries
Module Synthesis
Place/Route
Chip Assemblers
Silicon Compilers
Experts
Logic design
Electronic/circuit design
Device physics
Artwork
Applications - system design
Architectures

21. New Design Methodologies
Methodologies which are based on:
System Level Abstractions v.s. Device Characteristic Abstractions
Logic structures and circuitry change slowly over time
trade-offs do change, but the choices do not
Scalable Designs
Layout techniques also change slowly.
But the minimum feature size steadily decreases with time (also Voltage, Die Size, etc.)

22. Design Approaches Custom Semi-custom (std cell) Gate Array
full control of design
best results, slowest design time.
Semi-custom (std cell)
use Cell libraries from vendor
cad tools, faster design time
Gate Array
fastest design time
worst speed/power/density
best low volume (worst high volume)
EPLA/EPLD - FPGA - electrically programmable (in the field) -

23. Close up of Intel Chip?
Time Magazine, July 1998

24. Evolution in Speed/Performance
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

25. Technologies Bipolar (BJT) Dual Junction, current controlled devices
TTL, Schottky
ECL
I^2 L
Dual Junction, current controlled devices
MOS (FET unipolar)
NMOS, PMOS
CMOS <== our course
Single Junction voltage controlled devices
GaAs (typically JFET’s)
OEIC’s - MQW’s, Integrated Lasers,?

26. Silicon in 2010 Die Area: 2.5x2.5 cm Voltage: 0.6 V
Digital Integrated Circuits
© Prentice Hall 1995
Introduction
Die Area: 2.5x2.5 cm
Voltage: 0.6 V
Technology: 0.07 m

27. SIA -National Technology Roadmap for Semiconductors

28. SIA -National Technology Roadmap for Semiconductors
8 inch
18 inch

29. SIA -National Technology Roadmap for Semiconductors

30. SIA -National Technology Roadmap for Semiconductors

31. SIA -National Technology Roadmap for Semiconductors

32. SIA -National Technology Roadmap for Semiconductors