1. THE CMOS INVERTER

2. One cell, many possible layouts
PRINCIPLES
One cell, many possible layouts
The CMOS inverter design is detailed. Here one p-channel MOS and one n-channel MOS transistors are used as switches.
When the input signal is logic 0, the nMOS is switched off while PMOS passes VDD through the output, which turns to 1. When the input signal is logic 1, the pMOS is switched off while the nMOS passes VSS to the output, which goes back to 0. The n-channel MOS symbol is a device that allows the current to flow between the source and the drain when the gate voltage is "1".
The analog simulation of the circuit is performed.
The truth-table is verified. A logic zero corresponds to a zero voltage and a logic 1 to a 1.20V.

3. Various types of contacts
MANUAL DRAWING
Connect layers
Various types of contacts

4. MANUAL DRAWING
MOS from the library

5. Various types of contacts
MANUAL DRAWING
Connect layers
Various types of contacts

6. ADD A WELL POLARIZATION
Well polarization contact (VDD)
N-diff can touch P-diff but should not overlap
N-diff in N-well

7. Add supply, ground, a clock on input, an eye on output
INVERTER SIMULATION
Add supply, ground, a clock on input, an eye on output

8. INVERTER SIMULATION
The output (s1) is the exact invert of the input (clock1)

9. INVERTER SIMULATION
Current consumption at each output transition

10. New item “Manual Simulation”
INVERTER SIMULATION
New item “Manual Simulation”
2D cross-section of “cmos.MSK”

11. New item “Manual Simulation”
INVERTER SIMULATION
New item “Manual Simulation”
Node potentials are drawn with a palette of colors
Up to 3 inputs may be controlled
Voltage color palette
If it exists, the channel appears in blue below the gate

12. “Manual Simulation” enables direct control of inputs
INVERTER SIMULATION
“Manual Simulation” enables direct control of inputs
Click “Run Simulation” to update node values & channel aspects
Click “Run simulation” to update voltages
Input “A” is 0V (black)
No channel in the nMOS
A channel exists in the pMOS
Output “na” is VDD
(white)

13. Output is also near VDD/2
INVERTER SIMULATION
Switching point : Output is near VDD/2 when input is near VDD/2
Input is VDD/2 (red)
N-channel
P-channel
Output is also near VDD/2

14. INVERTER SIMULATION
Input is VDD, output is VSS
Input is VDD (white)
Output is VSS (black)
N-channel only

15. DELAY VS. FANOUT Fill the table Simulation of fanout 1, 2, 4 Fanout
Rise time
Fall time
THE INVERTER

16. Time domain simulations
USE OF PARAMETRIC ANALYSIS
You must ensure the clock frequency and simulation times are large enough for large capacitance
Time domain simulations
THE INVERTER

17. THE INVERTER DELAY VS. INTERCONNECT LENGTH
Interconnect is also a large capacitance load, and also a resistance
Charge increases with the interconnect length (interconnect parasitic capacitance)
Propose a RC model
The inverter delay is significantly increased.
It can be seen that the gate delay variation with the loading capacitance is quite linear.

18. INTERCONNECT MODELS
The tool Analysis > Interconnect Analysis gives detailed values of R, L and C
R the order of 1Kohm/mm
C the order of 50 fF/mm

19. THE INVERTER DELAY VS. INTERCONNECT LENGTH
Simulation shows very huge delays and a difference between near and far end
Buffering may be used to avoid RC delays, by inverter insertion

20. CURRENT CONSUMPTION 0.2 mA 0.2 mA for around 10 gates seems small …
..; but modern CPUs require millions of gates
This may lead to 100 A peak currents
0.2 mA

21. Student contest: fastest simulation
RING OSCILLATOR
THE INVERTER
Unstable by construction
Natural very high frequency oscillation t t t
Student contest: fastest simulation A
An illustration of the frequency increase with the technology scale down is proposed using a ring oscillator made from 5 inverters. This very simple circuit has the property to oscillate naturally. We observe the oscillating output and measure its corresponding frequency.
Although the supply voltage (VDD) has been reduced (VDD is 5V in 0.8µm, 2.5 in 0.25µm, 1.2V in 0.12µm), the gain in frequency improvement is significant. B

22. THE INVERTER RING OSCILLATOR
Almost x 100 in ring oscillation frequency from early 0.8µm technology to 32nm technology
An illustration of the frequency increase with the technology scale down is proposed using a ring oscillator made from 5 inverters. This very simple circuit has the property to oscillate naturally. We observe the oscillating output and measure its corresponding frequency.
Although the supply voltage (VDD) has been reduced (VDD is 5V in 0.8µm, 2.5 in 0.25µm, 1.2V in 0.12µm), the gain in frequency improvement is significant.