1. EE415 VLSI Design DYNAMIC LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. EE415 VLSI Design Dynamic CMOS l In static circuits the output is connected to either GND or V DD via a low resistance path. »fan-in of n requires 2n (n N-type + n P-type) devices l Dynamic circuits use temporary storage of signal values on the capacitance of high impedance nodes. »requires on n + 2 (n+1 N-type + 1 P-type) transistors

3. EE415 VLSI Design Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)

4. EE415 VLSI Design Conditions on Output l Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. l Inputs to the gate can make at most one transition during evaluation. l Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

5. EE415 VLSI Design Properties of Dynamic Gates l Logic function is implemented by the PDN only »number of transistors is N + 2 (versus 2N for static complementary CMOS) l Full swing outputs (V OL = GND and V OH = V DD ) l Non-ratioed - sizing of the devices does not affect the logic levels l Faster switching speeds »reduced load capacitance due to lower input capacitance (C in ) »reduced load capacitance due to smaller output loading (C out ) »no I sc, so all the current provided by PDN goes into discharging C L

6. EE415 VLSI Design Properties of Dynamic Gates l Overall power dissipation usually higher than static CMOS »no static current path ever exists between V DD and GND (including P sc ) »no glitching »higher transition probabilities »extra load on Clk l PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn »low noise margin (NM L ) l Needs a precharge/evaluate clock

7. EE415 VLSI Design Issues in Dynamic Design 1: Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Leakage is dominated by the subthreshold current

8. EE415 VLSI Design Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

9. EE415 VLSI Design Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

10. EE415 VLSI Design Charge Sharing Example C L =50fF Clk AA B B B!B CC Out C a =15fFC c =15fFC b =15fFC d =10fF

11. EE415 VLSI Design Charge Sharing B  0 Clk X C L C a C b A Out M p M a V DD M b Clk M e as C L V DD =C L V OUT + C a V OUT V OUT = V DD C L / (C L +C a ) V x increases up to V DD -V Tn when C a is small comparing to C L V x increases less up to V OUT when C a is larger Assume that initial voltage V x =0 and V out =V DD

12. EE415 VLSI Design Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

13. EE415 VLSI Design Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 When In goes up from 0 to VDD, output of static NAND gate ( Out2 ) goes down from VDD to 0 and pulls down Out1 through the capacitive coupling

14. EE415 VLSI Design Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2

15. EE415 VLSI Design Issues in Dynamic Design 4: Clock Feed Through CLCL Clk B A Out MpMp MeMe Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

16. EE415 VLSI Design Clock Feed Through Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feed through More noise is generated as a result of clock coupling

17. EE415 VLSI Design Other Effects l Capacitive coupling between output wires pulls down prestored charges l Substrate coupling l Minority charge injection l Supply noise (negative ground bounce may discharge the output)

18. EE415 VLSI Design Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 t V Clk In Out1 Out2 VV V Tn Only 0  1 transitions allowed at inputs! So do not connect these gates directly Output signal loss

19. EE415 VLSI Design Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1  1 1  0 0  0 0  1 Here we guarantee proper 0 to 1 transitions between gates

20. EE415 VLSI Design Why Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

21. EE415 VLSI Design Properties of Domino Logic l Only non-inverting logic can be implemented l Very high speed »static inverter can be skewed, only L-H transition so make PMOS of inverter stronger »Input capacitance reduced so smaller logical effort

22. EE415 VLSI Design Designing with Domino Logic

23. EE415 VLSI Design Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

24. EE415 VLSI Design Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off

25. EE415 VLSI Design np-CMOS Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 Possible coupling in longer runs to dynamic node

26. EE415 VLSI Design NORA Logic WARNING: Very sensitive to noise! In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 to other PDN’s to other PUN’s use np-CMOS blocks