Spring 08-Winter 09 semester Satellite Inner communication – SpaceWire & CAN Bus By: Michael Tsitrin, Asaf Modelevsky Instructor: Ina Ravkin הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות Midterm report Project name:

Spring 08-Winter 09 semester Goals to accomplish in the Project  Implement a SpaceWire host interface to the Amba AHB bus of a SoPC system with Leon3 processor. This host will connect to SpaceWire port that is already exists.  Simulate the implementation in Modelsim.  Test the SpaceWire core in a closed loop.  Test the SpaceWire core by communicating with another system using SpaceWire physical link.

Spring 08-Winter 09 semester The LEON3 system including SpaceWire Core AMBA AHB

SW port description  The SW port follows the E50-12A specifications for a SpaceWire Link.  The SW port provides a physical link interface towards the outside world and a control interface toward the host in which the port relies.  The Network Level in which the SpaceWire port operates is “Network Level 2” (Character Level). Therefore, such a SpaceWire port can be commanded to transmit only SpaceWire characters. Therefore, such a SpaceWire port can be commanded to transmit only SpaceWire characters.  The SW design was developed entirely in a XILINX environment and implemented by using XILINX library IP’s. Spring 08-Winter 09 semester

The SW port we integrate to the system Spring 08-Winter 09 semester

The SW port architecture Spring 08-Winter 09 semester

Current stage of implementation: Minimal System Spring 08-Winter 09 semester AMBA AHB SLAVE BUS Host interface (From AHB bus to SW port) SW Port Other SW link interface (Already exists) Our mission  We start our implementation with basic configuration: SW AHB slave interface, with small packets of data to exchange directly with LEON3 processor.

Host interface block diagram Spring 08-Winter 09 semester Signals to AHB Signals to SW Port

The FSM of the AHB interface Spring 08-Winter 09 semester

Basic test of the system SW core AMBA AHB BUS Dout Sin Din Sout  We will write a data chunk to the SW core, and than we will read from it. We should read the same data we wrote.

Spring 08-Winter 09 semester Advanced test of the system SW link interface SW core Board with LEON3 system Test equipment with SW interface  We will try to transfer complete files from the Leon3 system to the test PC over the SpaceWire physical link.

Current minimal system Vs. Final system  Minimal system:  Reading data from SW is done only by processor’s request.  Data transfer rate is limited by FIFO’s size because of slow AHB bus transactions (assumption, not tested yet).  Simple implementation.  Final system:  Reading from SW will be done by a more complex interface, based on DMA engines or Interrupt mechanism.  Implementation will relay on SW interface as described in GRLIB manual. Spring 08-Winter 09 semester

Implementation of SW interface as described in GRLIB manual  The SW AMBA interface consists of AHB Master interface and DMA FIFO’s.  The DMA engines have 32-bit wide FIFO’s which used for reading and writing on the AHB.  Receiver and Transmitter DMA’s write/read at half the FIFO’s size bursts. Spring 08-Winter 09 semester

Present stage of project  Successfully connected the SW minimal configuration to the LEON3 system.  When connected in closed-loop SW core recognized the connection and moved to “run” state.  Data from LEON3 processor transferred successfully through the SW transmitter, closed loop and to the SW receiver.  Our next step is to to read the data from the receiver and compare it with the sent data. Spring 08-Winter 09 semester

Time table  Until the end of December - finish simulating the minimal configuration with ModelSim.  Until beginning of February - debugging of the complete minimal system with GRMON, while communicating with SW test equipment.  Beginning of March - final report and preparation for the next semester - designing the final system architecture. Spring 08-Winter 09 semester