1. Performed by:Gidi Getter, Shir Borenstein Supervised by:Ina Rivkin Final Presentation 21/07/2008 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Space Wire Core for LEON3 System

2. Project Definition Design a Space Wire core for LEON3 system. Load Leon3 system with our own IP core to GR-RASTA board.

3. What is Space Wire? Space Wire is a spacecraft communication network. It is coordinated by the European Space Agency (ESA). Components are connected through low-cost, low- latency, full-duplex, point-to-point serial links. Uses data strobe encoding - differential ended signaling (DS-DE). Space Wire utilizes asynchronous communication and allows speeds between 2Mb/s and 400Mb/s. The protocol describes routing, flow control and error detection in hardware, with little need for software.

4. The Protocol Consists of Data characters and Control characters. Data characters are 10 bits long – 1 parity bit, 1 flag bit set to ‘0’ and 8 data bits.

5. The Protocol Control characters are 4 bits long – 1 parity bit, 1 flag bit set to ‘1’ and 2 control characters. Control codes is built with the ESC character following a FCT character / Data character.

6. Space Wire Usage SW SW Router Component A (Computer, Device, etc) Satellite Component B

7. LEON3 System LEON3 Processor AMBA AHB Bus AHB Controller JTAG Dbg Link Memory Controller SERIAL Dbg Link JTAGRS232 Space Wire Link LVDS RAM SRAM, DRAM etc.

8. Space Wire Core – Top Level

9. Space Wire Core – Controller gotFCT ‘1’ Q ctrl_rst clk DQ ctrl_rst DQ D

10. Space Wire Core – Transmitter Data serialization unit – translate the character into data-strobe logic values clk tick tr_clk tick_tr FCT synchronizer req ack Early data fetch from FIFO Transmitter control unit – decides which character to transmit and manages FCT balance

11. Space Wire Core – Receiver 01001000 clk D Serial to parallel character decoder Initialization Null decoder DCM & reset generator State controller and timer Time code synchronizer FCT synchronizer Clock restore

12. Leon3 reads data one packet at a time. All NChars are forwarded from FIFO1 to FIFO2 until EOP/EEP is detected. No further data is written into FIFO2 until is the packet was read by Leon3 and FIFO2 is empty again. Receiver FIFO

13. Handles all requests from processor. Reads and writes data from FIFOs to transfer between core and processor. Add bit for data/EOP. Updates Status Register. Informs available room in receive FIFO for FCT handling by transmitter. State Machine Status Register clk reset AHB_slave_in AHB_slave_out wr_en Data 9 rd_en Data 8 Tick_out Time_in AMBA AHB Controller Tick_in Time_out

14. The Space Wire core with Leon3 system was checked in logic simulation only. The Leon3 system with a custom IP core was loaded into GR-RASTA board. Coming up next: Simulation results. Logic Simulation

15. Logic Simulation – Transmit The value of the status register is sent back to the processor. The processor initiate a read cycle on the bus, to the write status register address. volatile int *check_status = 0xB0000ABC; free_space = 64 - *check_status;

16. volatile int *send_addr4 = 0xB0000000; *send_addr4 = *nchar; Logic Simulation – Transmit Data is written into transmit FIFO. 4 write cycles to transfer 4 nchars. Transmitter reads the nchars from the FIFO Transmitter sends the nchars across the link

17. Logic Simulation – Receive Receiver detectes arrival of nchar on link. The nchars are written into FIFO 1. Data is transferred from FIFO1 to FIFO2 as long as EOP was not recieved Status register in AHB controller is updated by the number of nchars stored in FIFO2.

18. Logic Simulation – Receive Receiver detectes arrival of EOP A character marking arrival of EOP is written to reciever FIFO1 FIFO controller reports arrival of EOP to AHB controller. No more nchar will be tranfered to FIFO2. AHB status register is updated, to report arrival of EOP to processor.

19. Logic Simulation – Receive The rest of the computation is done in software The value of the status register is sent back to the processor. The processor initiate a read cycle on the bus, to the status register address. volatile int *check_status = 0xB0100AB0; status = *check_status;

20. Logic Simulation – Receive The processor requests to read 4 nchars The AHB controller reads 4 lines from receiver FIFO and collects them The data is sent back to the processor, 4 nchars in parallel (32 bit data bus)

21. LEON3 design configuration. Add instantiation of the core to leon3mp.vhd (top module). Add VHDL file list of the core to Makefile. This will add the files to simulation and synthesis scripts. Write C code of the program. Compile using sparc-elf cross compiler. Create an exec file to run on board, and a memory snapshot for simulation. Simulate design using testbench provided by gaisler. Perform synthesis with synplify, using generated script. Perform P&R with ISE tool, and load bit file to board. Load exec file and run program using GRMON. Configuring LEON3 System

22. Add support for UART and DSU. LEON3 Design Configuration

23. Add support for UART and DSU. LEON3 Design Configuration

24. Add support for UART and DSU. LEON3 Design Configuration

25. Add IP Core Add instantiation of the core to leon3mp.vhd (top module).

26. Add IP Core AHB slave index number on the bus 12 MSB bits of slave address space Number of AHB slaves on the bus. Default is 8, change to 16.

27. Makefile Add the VHDL files of the core to “VHDLSYNFILES” parameter

28. Testbench Change SDRAM file to the same as SRAM file.

29. Create scripts for Simulation “make scripts” command generates tool-specific compile scripts. “make vsim” compiles all VHDL files and testbench for simulation. “make xgrlib” – GUI interface for running these commands and more.

30. Compile C Program for LEON3 Compile C code using sparc-elf cross compiler: To create an exec file to run on board: sparc-elf-gcc -O2 -g prog.c -o prog.exe To create a memory image for simulation: sparc-elf-objcopy -O srec prog.exe sram.srec

31. Simulation and Synthesis Simulate design with Modelsim: run “make vsim” will compile all the files. Run synthesis: “make synplify” will create a project file (leon3mp_synplify.prj) for Synplify. These commands can be run from xgrlib GUI.

32. P&R with ISE Can be run directly from synplify after synthesis. Constrains file to be used in ISE is provided in the LEON3 package in: “boards\gr-cpci-xc2v\leon3mp.ucf”

33. Problems Using GR-CPCI-XC2V Bit files can be programmed from PROM or Boundary Scan (JTAG). By default, the board is configured to be loaded from PROM at startup. To load a new bit file, the system must be reset. If a new bit file is loaded again before reset, the new system will not function.

34. Problems Using GR-CPCI-XC2V To configure the board to be loaded only from JTAG, set jumpers to Boundary Scan Programming (Mode='101').

35. LEON3 Debug Support Unit

36. RS232 DSU connection for serial connection to PC JTAG connection for loading and debugging

37. GRMON GRMON is a general debug monitor for the LEON processor. Can be used to access all system registers and memory. Used for downloading and execution of LEON applications. Can access the DSU via RS232, JTAG, PCI, USB and ethernet. Can loopback UART in system and print its output on console.

38. GRMON Starting GRMON: With UART loopback via serial: grmon -u With UART loopback via JTAG: grmon -u -jtag GRMON command-line interface: Load a program: load To run a program: run System information: info sys Displaying register content: reg Displaying memory contents: mem

39. GRMON

40. Achievements & Future Development Project main steps: Learn and implement Space Wire protocol. Integrate SW core into LEON3 system. Operate GR-CPCI-XC2V board with LEON3 system with our own IP core. Future improvements: Operate the SW core on the board with loopback, and check compatibility of protocol with SW bridge. Integrate SW core as master on AHB bus, implement interrupt and DMA for transactions.