1. Performed by: Moshe Emmer, Harar Meir Instructor: Alkalay Daniel Cooperated with: AE faculty המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו”ח סיכום פרויקט סופי Cube-Sat On Board Computer 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 A satellite in-advance design and daily operation demand a multidisciplinary approach and a highly practical implementation. One of the issues that is highly involved while designing a satellite is the electronic functioning. As a matter of a fact, wisely implementing an OBC (On Board Controllers) is a crucial part in building a satellite, since it directly carries out the different tasks. Architecture of such has to be decided and configured while many inputs are given. Only by taking under consideration all engineering aspects one can create a strong, liable and smart implementation.

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 A System, consists of 3 MicroBlaze and a Watch Dog was built up. The three MicroBlazes serves as individual processing units, while managed by one of them – MB0. All units are connected in a closed, Bi-directional loop, which guarantee smooth data transferring

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 In order to implement the architecture we chose, we used the following building blocks: 1.low level controller (FSM), 2.3 32-bit microcontroller (uBlaze). 3.6 FSL busses. 4.8K/64K data and instruction, BRAM memory array 5.Uart on OPB connected to a MicroBlze, The system contains three soft-cores. Each processor (Microblaze0, Microblaze1, Microblaze2) is an independent core. A unique C-code program was designed for every processor. Microblaze0, for example, is the only processor which is connected to the HyperTerminal (through UART module). The OPB (On-chip peripheral bus) can contain only one master, and therefore only one processor can communicate with the UART (RS232, Leds, Switches, etc are slaves). Two different arithmetic functions (division and subtraction) are operated by Microblaze1 and Microblaze2, accordingly. The data is transferred between the processors using blocking read/write functions that use the FSL modules. The blocking read and write keep the processors synchronized with each other. In addition, a macro-function was written to enable the transmission of multi-packets on the FSL between Microblaze0 and Microblaze1.

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

6. Summary Design must first start in the architecture abstract level, especially when using FPGA technology In a system of various tasks, each can be implemented by an independent controller, while all will be communicating according to a protocol, defined by the designers On 1 Virtex-4, FPGA chip, one can implement many independent processing units; such as MicroBlazes, PicoBlazes, FSMs and other hardware modules. All can carry out different tasks and exchange data using a Fast, simple method – FSL bus It is also possible to break one mission into N different processes, using N different cores and raising performance by N*100 % (upper bound value!)

7. Summary FSL is a FIFO, 1-way bus that can smoothly answer any communication needs of the processing units. It can be activated either under a non-blocking or a blocking regime. Each, of course has its own advantages and disadvantages. blocking is the simple way, giving fast and un-complex design Think of the endless opportunities! With a FPGA chip and a good understanding of the architecture one can gain boost in performance of a process by using parallel cores!

8. Summary A system using MicroBlaze and FSL links to communicate between them has been developed, and with the experiments tested it can be concluded that the FSL links are an ideal choice for exchanging data between processors due to their high speed data transfer rates Analysing the synthesis results, it is clear that what limits the number of processors in a multiprocessor design on FPGA is the amount of BlockRAM available, not the total size of the FPGA.

9. Summary Completely Meshed A completely meshed network is a network in which each node is connected to every other node in the network. It is a good way to reduce the traveling time of packets over a network, because data goes directly from sender to receiver, but its main disadvantage is that the number of links grows extremely quickly when the number of nodes is increased. A completely meshed network topology with MBlaze and FSL links will only be possible for just 9 MBlazes, because of the limitation of 8 FSL links for each MicroBlaze processor.

10. Summary Ring Network A ring network is a network in which each node in the network is connected to the following and the preceding node in the network, forming a ring. Data is passed from node to node until it reaches the destination node. With MBlaze and FSL links there will not be a size limit for the network, because each MBlaze would just use 2 FSL links. The main problem of this topology is that data transfers from two nodes that are far from each other are very time consuming.