1. Performed by: Oron Port Instructor: Mony Orbach המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Project Characterization Subject: Jitter Generator Winter 2006/7 1

2. Project Definition המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Extension of the project “Jitter experiment”, performed by Gregory Zabolotov during Spring 2005 semester. Developing GUI-based software for an easy user control of the deterministic jitter applied on a fed clock.

3. What is Jitter? המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Jitter is the short term variation of the significant instants of a digital signal from their ideal positions in time.

4. Existing Hardware המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Hardware developed for the Vertex II Pro board extension slot. Using a Programmable Delay Chip (PDC), it is possible to define a delay between 2.2nsec and 12.2nsec (in 10psec increments) for a given clock signal. Changing the delay continuously and periodically creates a deterministic periodic jitter effect. The JG board is connected to the SOPC data bus. Vertex II Pro board PDC Jitter Generator (JG) PCB Extension slot

5. Project Implementation המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Interface #1: MMI – Man-Machine-Interface GUI – Graphical-User-Interface Vertex II Pro board RS-232 SOPC E x t e n s i o n s l o t Jitter Gen. Data Bus

6. Project Implementation המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Interface #2: RS-232 communication (Ethernet is optional)  * Transferring a jitter period’s data selected in interface #1 to the SOPC’s memory, and other commands according to what was selected. Vertex II Pro board RS-232 SOPC E x t e n s i o n s l o t Jitter Gen. Data Bus

7. Project Implementation המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Interface #3: SOPC Data bus  Updating the PDC on the JG board with the current delay time, according the tables filled in the SOPC’s memory during interface #2. Vertex II Pro board RS-232 SOPC E x t e n s i o n s l o t Jitter Gen. Data Bus

8. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Clock is provided differentially to the JG board using two SMA connectors. Jittered output from the JG board is the same. Software Will be developed in Visual C++.NET GUI. Will have the capability to choose either built-in jitter period (already defined in the SOPC) or dynamically upload a jitter period to the SOPC’s memory (10 typed of signals). 4

9. Time Table המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Week # DatesActionComments 1-25.11.06 - Lab introduction, initial project planning. 18.11.06 319.11.06 - Characterizing project requirements. 25.11.06 4-526.11.06 -Miluim 9.12.06 610.12.06 - Interface #1: GUI Creation Interface #2,3: Learning how previous project worked and tested. Project Characterization Presentation 16.12.06

10. Time Table המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Week # DatesActionComments 717.12.06 - Interface #1: Complete. Interface #2: Computer’s software end complete. 23.12.06 8-1024.12.06 - Learn how to program the SOPC. Interface #2: SOPC’s end complete. Interface #3: Initial trial & error. Midterm Presentation 13.01.07 11-1314.01.07 - Interface #3: Complete. Testing the project as a whole. 03.02.07 14- FP 04.02.07 - Finalizing documentation until final presentation, submitting files and final report, Final Presentation 06.03.07