1. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering 1 Performance Analysis of Processor Performed by: winter 2005 Alexei Iolin 307724211 Alexander Faingersh 306966912 Instructor: Evgeny Fiksman

2. Abstract & Project Goals המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 MicroBlaze is a Soft Core Processor developed by Xilinx that meets performance, area-efficiency and low cost targets. Although using the MicroBlaze enables fast system development on a single FPGA, some of the “special” applications run slower than in Hard Core Processor. We will examine this with EDK environment and try to accelerate the SW with hardware IP. Examination of MicroBlaze calculation abilities by measuring time of running applications and examining Interrupt handler abilities. Measuring power consumption by sampling current during program executions (LabView). Implementing arbitrary application in Hardware (IDCT) and using it as a hardware acceleration for MicroBlaze. Implementing the same functionality in C and comparing the results with hardware. Adding self written C code for testing FPU.

3. MicroBlaze OPB Peripherals המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3

4. Arbitrary IP (VHDL) on FSL bus המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 4

5. Example for Time & Current Measurements המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

6. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 ApplicationMean initial and eternity current [a] Mean program current [a] Max program current [a] TimeMean Power [mw] Mean Energy [ujoule] IDCT SW Fixed point 0.16830.16490.2253320.31 usec ~ 25080 IDCT SW Floating point 0.25040.19530.271493.66 msec ~ 35032781 IDCT HW Fixed point (FSL) 0.21130.16140.222512.31 usec ~ 2803.45 MicroBlaze is a very effective solution for easily configurable systems demands. Distinguishing critical passes and implementing them in HW can greatly decrease execution time. FSL is the most effective (energy and time) way for connecting HW acceleration to MB. FPU is the most problematic consumer. Massive use of FPU is not recommended in MB. Interrupts input frequency is maximum 890kHz. Conclusions