Front-End electronics for Future Linear Collider calorimeters C. de La Taille IN2P3/LAL Orsay On behalf of the CALICE collaboration

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 2 « Imaging calorimetry » at ILC Particle flow algorithm Reconstruct each particle individually Bring jet resolution down to 30%/√E Measure charged particles in tracker Measure photons in ECAL Measure hadrons in ECAL and HCAL Minimize confusion term Calorimeter design High granularity : typ < 1 cm 2 High segmentation : ~30 layers Moderate energy resolution (10%/√E) ECAL : Silicon-Tungsten HCAL : analog vs digital CALICE collaboration « a high granularity calorimeter optimized for particle flow algorithm 190 phys./eng., 9 countries, 3 regions ©J.C Brient (LLR) F. Sefkow (DESY)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 3 ILC Challenges for electronics Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : ( « 100µW/ch ) 10 8 channels Compactness « Tracker electronics with calorimetric performance » ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/chILC : 100µW/ch W layer Si pads ASIC Ultra-low POWER is the KEY issue

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 4 CALICE physics prototype(s) 1 m 3 prototype for physics tests Goal : study particle flow algorithm Check modelization of hadronic showers 3 calorimeters to go to testbeam ECAL : W-Si 24X 0 20x20 cm 2 AHCAL : Tiles + fibers + SiPMs DHCAL : RPCs or GEMS Already 10 4 to channels ! Run at DESY (05), CERN (06), FNAL (07)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 5 14 layers, 2.1 mm thick 70 boards made in Korea ECAL W-Si prototype ECAL prototype 1 cm 2 Si PADS, 550 µm 1 MIP = e- 216 channels/slab channels total Readout electronics FLC_PHY3 ASIC [LAL] Calibration ASIC [LAL] CRC DAQ boards [UK]

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 6 FLCPHY3 front-end ASIC Amp OPA G1 G10 1 channel Chip architecture 18 Channels/chip Low noise charge preamp optimized for Cd=70pF. Variable gain (Cf = 0.2 -> 3 pF) ENC = 1000e tp=200ns series noise : en = 600 µA poor 1/f noise : 25 e-/pF Dual gain shaper (G1-G10) tp = 200 ns splits 15bit dynamic range in 2 x 12 bits Differential shaper and Track&Hold => better pedestal stability and dispersion : pedestal dispersion : 5 mV rms Multiplexed output : 5 MHz Power dissipation : 6mW/channel Technology : AMS 0.8µm BiCMOS 2000 chips produced in 2003, yield : 86% Synoptic of 1 channel of FLCPHY3 ©J. Fleury (LAL)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 7 FLC_PHY3 : performance Measured on all preamp gains Cf = 0.2, 0.4, 0.8, 1.6, 3 pF Well within ± 0.2 % Dynamic range (G1, C f =1.6pF) Max output : 3 V linear (0.1%) range : 2.5V = 500 C f = 1.6 pF Noise : 200 µV (Cd = 0) 410 µV (Cd = 68pF) = 0.1 C d = 68 pF Dynamic range : > 12 bits (14 Cd = (12 Cd = 68 pF Can be extended to bits by using the bi-gain outputs

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 8 Results with detector Testbeam at DESY (jan 05) Calorimeter partially equipped (7 X 0, 3000 channels) MIP/noise = 8 => clean cut at ½ MIP Calibration done with cosmics Just now completed to 24X 0 ! Noise, MIP 2 adjacent 2 GeV electrons ©G. Gayken (LLR)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 9 AHCAL testbeam prototype 1 cubic metre, 38 layers, 2cm steel plates 8000 tiles with SiPMs Electronics based on ECAL design Mechanics and front end boards: DESY Front end ASICs: LAL ©F. Sefkow (DESY)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 10 SiPMs for calorimetry Multipixel Geiger Mode APDs –Gain 10 6, bias ~ 50 V, size 1 mm 2 –Insensitive to magnetic fields 3x3 cm scintillator tile with WLS fibre ITEP 1156 pixels with individual quenching resistor on common substrate MEPHI / PULSAR Auto-calibrating but non-linear New era for scintillator– based detectors: High granularity at relatively low cost

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 11 Variable Gain Charge Preamplifier Variable Shaper CR- RC² SiPM readout ASIC Readout AHCAL (DESY) SiPM detector (MEPHI ) >3000 channels : first large scale use G ~ 10 6 e ~10% HV ~ 50 V FLC_SiPM readout ASIC 18 channel variable gain preamp and shaper Dynamic range : 13 bits (2 gains) 8 bit DAC for SiPM gain adjustment 1000 chips produced in 2004 One pixel signal © E. Popova Single photoelectron spectrum © E. Popova ©L. Raux (LAL)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 12 Digital HCAL physics prototype GEM based DHCAL RPC based DHCAL Signal Pad Mylar sheet Aluminum foil 1.1mm Glass sheet Resistive paint 1.2mm gas gap -HV GND Charged particles ©A. White (U. Arlington) J. Repond (ANL)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 13 DHCAL front-end electronics ©J. Hoff, A. Mekaoui (FNAL) DCAL chip 64 inputs with gain choice GEM/RPC Triggerless or triggered operation Output hit pattern & time stamp Prototyped in 0.25µm in march 2005

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 14 DCAL chip performance All digital functions operationnal Excellent efficiency curves Threshold adjustable between 2-8 fC DCAL2 chip Submission foreseen july 06 Reduced preamp gain Threshold RPC ~ 100 fC Threshold GEMS ~10 fC

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 15 Technological prototype : “EUDET module” Front-end ASICs embedded in detector Very high level of integration Ultra-low power with pulsed mode FLC_TECH1 ASIC prototype in 0.35 µm SiGe All communications via edge 4,000 ch/slab, minimal room, access, power small data volume (~ few 100 kbyte/s/slab) « Stitchable motherboards » Elementary motherboard ‘stitchable’ 24*24 cm ~500 ch. ~8 FE ASICS

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 16 EUDET module FEE : main issues Mixed signal issues Digital activity with sensistive analog front-end Pulsed power issues Electronics stability Thermal effects To be tested in beam a.s.a.p. No external components Reduce PCB thickness to < 800µm Internal supplies decoupling FE chip (1mm) Wafer (400µm) PCB (600µm) Tungsten (1 mm)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 17 ECAL Front-End ASIC Power Cycling Auto-trigger on ½ MIP Internal ADC Readout integration is the key element of compact detector Keep small Moliere radius for good shower separation Many features have never been used before e.g. power cycling (ON 2ms OFF 200 ms)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 18 Present status on noise & power cycling FLC_TECH1 : moving into SiGe 0.35µ 30 µW in pulsed mode ENC = 1000 Cd=27pF (MIP= e -)  NOISE WELL BELOW MIP First demonstration of power cycling : Target power of 100 µW/channel appears within reach : to be validated in testbeam in 2006 with FLC PHY4 ASIC FLC shaping Detector capacitance Autotrigger ON signal Ready for pulse RFCFRFCF 20 µs POWER CYCLING MEASUREMENT NOISE MEASUREMENT

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 19 EUDET ECAL ASIC 72 channels Scales with the 4 factor reduction in pad size and is compatible with physics prototype Detector DC coupling Prepares the case the on-detector MMIC HV capacitance is not affordable Provides leakage current monitoring, up to 1 µA/Ch Auto-trigger If one channel is hit during a bunch crossing, then the whole chip is recorded with a time tag (BCID) The auto trigger activates the T&H Analogue pipeline, ADC & digital registers 8-depth analog pipeline to store « in bunch » events Wilkinson 12 bit 100MHz ADC On chip storage, inter-bunch data outputting Digital data output Daisy chained with redundancy : one output for 40 ASICs Common architecture for ECAL and HCAL

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 20 Front-end Derived from existing FLC_PHY4 chip To ADC – leakage current meas. SCA Bipolar Fast shaper Monostable Threshold Trigger Timewalk-free Vref_fs

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 21 ADC Channel 0 Channel 1 Channel 71 Ramp generator Register 0 Register 71 Gray counter Wilkinson architecture, developped by Clermont group 100 MHz clock frequency : 4 µs digitization time for 12 bits ©G. Bohner (LPCC)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 22 Digital part Store all channels and BCID for every hit. Depth ~8 bits Event size : 8(depth)*[16bit*72ch+16bit(bcid)] = 9344 bits Sequential readout : 9344*10ns = 100 µs : LVDS level Register 16bits OR 16 bit counter BCID Register 16bits Discri CH 0 Discri CH 71 Register 16*16 bit BCID

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 23 EUDET ECAL ASIC Will be submitted in AMS 0.35µm SiGe in sept 06 Area : 3 x 7 mm 36 Analog Channels + ADC 36 inputs 36 inputs Digital memory and controls 36 Analog Channels + ADC Control signals and power supplies

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 24 EUDET DHCAL RPC ASIC Move towards ILC specs Power pulsing Data internally saved during bunch train Data transferred to DAQ during inter-bunch Chip based on MAROC will be submitted in sep 06 Close to MAROC chip 64 channels for multi-anode PM

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 25 MAROC : 64 ch MAPMT chip for ATLAS lumi Characteristics 64 PMT channels input ( Ω) Variable gain current conveyor (0-2) 6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16 64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz Common threshold loaded by internal 10bit DAC 1 multiplexed charge output with variable shaping ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1% Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm 2 Dissipation 130 VDD=3.5V Can be accomodated to DHCAL Adding power pulsing and digital readout Synoptic diagramm of MAROC1 Hold signal Variab le Gain Pream p. Variable Slow Shaper S&H Bipolar Fast Shaper 64Trigger outputs Gain correction 6 bits/channel discriminator threshold 10 bits DAC Multiplexed charge output 64 PM inputs 10 bit DAC ©N. Seguin (LAL)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 26 « super common base » Preamplifier Current conveyor « Super common-base » configuration Low input impedance : 50 – 100 Ω Rin = 1/g m1 g m2 R C =V T 2 /I C1 I C2 R C + 50 Ω protection Can be varied by adjusting I C1 Low “Inductive term”(50 nH) with careful dimensioning Large output impedance : ~500 kΩ Unity current gain Q2 Q1 Rc Iin Iout

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 27 MAROC Efficiency curves

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 28 Prospective for A-HCAL SiPM Chip Similar developments for AHCAL Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing T&H x1 Variable gain Preamplifier Discri TDC 12-bit ADC 8 bit DAC (0-5V) in Fast Shaper Shaper t p ~30-40ns Auto-trigger 12-bit DAC Threshold Capacitance for AC coupling … Analogue Memory Charge Ouput Time Ouput

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 29 Conclusion Several large dynamic range ASICs developped for CALICE physics prototypes ECAL W-Si calorimeter : FLC_PHY3 = 10 4 channels in beam, dynamic range MIPS AHCAL Tile-SiPM calorimeter : FLC_SiPM = 10 3 channels installed, beam in summer 06 DHCAL GEM/RPC ASICs for technological prototypes now in development Power pulsing Zero-suppress Auto-trigger System aspects not to be forgotten Power supplies ! Mechanics Reliability…

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 30 Backup slides

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 31 SLAC-Oregon-UC Davis-BNL Si-W ECal R&D David Strom Effective 4 x 4 mm 2

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 32 SLAC-Oregon-UC Davis-BNL Si-W ECal R&D KPix Cell 1 of 1024 M.Breidenbach Tungsten Si Detector KPix Kapton Bump BondsMetallization on detector from KPix to cable Thermal conduction adhesive Kapton Data Cable Heat Flow

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 33 FLC_TECH1 : noise performance FLC_TECH1 : 0.35µm Series : e n = 1.4 nV/√Hz C PA = 7 pF 1/f noise : 12 e-/pF Parallel : i n = 40 fA/√Hz Target noise of ENC < MIP/10 = 4000 e- is (more than) achieved FLC_PHY3 : 0.8µm Series : e n = 1.6nV/√Hz C PA = 10pF + 15pF test board 1/f noise : 25e-/pF Parallel : i n = 40 fA/√Hz ENC vs shaping time FLC_PHY3 0.8µ ENC vs shaping time FLC_TECH1 0.35µ FLC shaping Detector capacitance Autotrigger

EUDET : ECAL emodule Electromagnetic calorimeter Prototype of a (~ 1/6) module 0 : one line & one column 150 cm long, 12 cm wide 30 layers channels Test full scale mechanics + PCB Can go in test beam Test full integration + edge communications Similar in #channels as physics prototype ©M. Anduze (LLR)

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 35 Digital part Store all channels and BCID for every hit. Depth ~16 bits Data format : 16(depth)*[1bit*128ch+16bit(bcid)] = 2 kbits Sequential 100 MHz : 2000 * 10 ns = 20 µs Register 16bits OR 16 bit counter BCID Register 16bits Discri CH 0 Discri CH 127 Register 16*16 bit BCID More probably a RAM

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 36 FLCPHY4 Ch Ch.2 Ch.18 Digital Output Multiplexing Gain 10 Multiplexing Gain 1 Idle Digital Output Integrating 12 bit ADC [collab LPNHE Paris] and full power cycling Submitted in july 05, to be validated in testbeam 06 at CERN 12 bit ADC ( AMS IP) Power Cycling

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 37 HCAL architecture Typical layer 2m tiles 38 layers tiles FEE: 32 ASICs (64-fold) 4 readout lines / layer Layer data Concentrator (control, clock and read FEE) Module data concentrator Instrument one tower (e.m. shower size) + 1 layer (few 1000 tiles) To DAQ EUDET: Mechanical structure, electronics integration: DESY and Hamburg U

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 38 Towards module0 ASIC : FLC_TECH No Power Cycling No Auto-trigger on ½ MIP No Internal ADC What is missing in FLC_PHY3 : Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel Dynamic range <1000 MIPS

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 39 Signal uniformity (G1) Signal (Gain 1, C f =1.6pF) Amplitude = 696 mV/pC ± 18 mV = 4.66 mV/ MIP ± 2.5% rms Peaking time = 189 ns ± 2 ns rms Pedestals = -3.7 V ± 4.8 mV rms Noise Cd = 0 pF : Vn = 200 µV Cd = 68pF : Vn = 410 µV Crosstalk : < 0.1% Gain 1 uniformity vs channel number Peaking time uniformityPedestal uniformity

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 40 Signal uniformity (G10) Signal (Gain 10, Cf=1.6pF) Amplitude = 6294 mV/pC ± 188 Peaking time = 174 ns ± 2 ns Pedestals = V ± 8.3 mV rms Noise Cd = 0 pF : Vn = 500 µV Cd = 68pF : Vn = 1.6 mV Crosstalk < 0.2% Pedestal uniformityPeaking time uniformity Gain 10 uniformity vs channel number

20 may 2006C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 41 as function of input charge Error bars = RMS of distributions Nice linear dependence! 2 nd Iteration of ASIC Prototype - Decrease of input sensitivity by x 100 Currently upper threshold corresponds to 7.6 fC Smallest RPC signals ~ 100 fC Noise from digital lines ~ 20 fC (preliminary) - Decouple of output clock and chip clock - Submission on July 22 nd (highest priority of FNAL design group) Redesign will start in late May - Will be used in slice test of Digital Hadron Calorimeter with RPCs (January 2007 at MT6) More Results… c) Linearity with injected charge d) Tests of pipeline e) Measurements of noise rate f) Tests of time stamp counter All successful!!!