1. Front-End electronics for CALICE Calorimeter review Hamburg
HaRDROC
SKIROC
SPIROC
Front-End electronics for CALICE Calorimeter review Hamburg
C. de La Taille
IN2P3/LAL Orsay
On behalf of the CALICE collaboration

2. CALICE Testbeam at CERN SPS
TCMT
AHCAL (3 000 ch)
W-Si ECAL (6 000 ch)
HCAL
SiPM ASIC
Imaging CERN
FLCPHY3 ASIC
Common DAQ ch
31 may 2007
C. de La Taille front-end electronics for CALICE

3. FLC_PHY3 readout ASIC [LAL]
Amp
OPA G1
G10
1 channel
Dual gain low noise charge preamps
Multiplexed analog output
Dynamic range > 12 bits
linear (0.1%) range : 2.5V = 500 Cf = 1.6 pF
14 layers, 2.1 mm thick
70 boards made in Korea
31 may 2007
C. de La Taille front-end electronics for CALICE

4. C. de La Taille front-end electronics for CALICE
Results with detector
©G. Gayken (LLR)
Testbeam at DESY (jan 05) and at CERN (2006)
Calorimeter complete in depth (24 X0, channels)
MIP/noise = 8 => clean cut at ½ MIP
Calibration done with cosmics
Noise, MIP
31 may 2007
C. de La Taille front-end electronics for CALICE

5. SiPM readout ASIC [LAL]
©L. Raux (LAL)
Readout AHCAL (DESY)
SiPM detector (MEPHI )
>3000 channels : first large scale use
G ~ 106 e ~10% HV ~ 50 V
FLC_SiPM readout ASIC
18 channel variable gain preamp and shaper
Dynamic range : 13 bits (2 gains)
8 bit DAC for SiPM gain adjustment
1000 chips produced in 2004
Power consumption : ~200mW (supply : 0-5V)
Technology : AMS 0.8 m CMOS
Chip area : ~10mm²
Package : QFP-100
Single photoelectron spectrum © E. Popova
31 may 2007
C. de La Taille front-end electronics for CALICE

6. DCAL chip for DHCAL [FNAL]
©J Repond (ANL)
64 channle ASIC
0.25µm
→ prototyped (40 chips in hand)
→ extensively tested at Argonne
→ tests complete
→ ordered additional chips
Reads 64 pads
Has 1 adjustable threshold
Provides
Hit pattern
Time stamp (100 ns)
Operates in
External trigger or
Triggerless mode
31 may 2007
C. de La Taille front-end electronics for CALICE

7. C. de La Taille front-end electronics for CALICE
DCAL chip performance
DCAL2 Testing I: Internal pulser
Good performance for both RPC and GEMS : ready for production
Threshold scans…
All channels OK, except
Channels #31/32 show some anomalies
(understood, no problem)
31 may 2007
C. de La Taille front-end electronics for CALICE

8. C. de La Taille front-end electronics for CALICE
DCAL2 Testing III: External pulser
Linear up to ~300 fC
Range up to ~700 fC
(RPC: Q = 100 fC ÷ 10 pC)
Corresponds to zero charge
(Offset in charge)
Q(fC) = 1.91·ADC
100 hits per point
Average threshold defined as ε=50% point
31 may 2007
C. de La Taille front-end electronics for CALICE

9. Next steps : technological prototypes
HaRDROC (2006)
FLC_PHY3 (2003)
31 may 2007
C. de La Taille front-end electronics for CALICE

10. Technological prototype : “EUDET module”
Front-end ASICs embedded in detector
Very high level of integration
Ultra-low power with pulsed mode
Target 0.35 µm SiGe technology
All communications via edge
4,000 ch/slab, minimal room, access, power
small data volume (~ few 100 kbyte/s/slab)
« Stitchable motherboards »
Minimal conncections between boards
Elementary motherboard ‘stitchable’ 24*24 cm ~500 ch. ~8 FE ASICS
31 may 2007
C. de La Taille front-end electronics for CALICE

11. EUDET module FEE : main issues
Mixed signal issues
Digital activity with sensistive analog front-end
Pulsed power issues
Electronics stability
Thermal effects
To be tested in beam a.s.a.p.
No external components
Reduce PCB thickness to < 800µm
Internal supplies decoupling
Low Cost and industrialization are the major goal
31 may 2007
C. de La Taille front-end electronics for CALICE

12. C. de La Taille front-end electronics for CALICE
Read out : token ring
Chip 0
Chip 1
Chip 2
Chip 3
Chip
5 events
3 events
0 event
1 event
Data bus
Chip 0
Acquisition
A/D conv.
DAQ
IDLE MODE
Chip 1
Acquisition
A/D conv.
IDLE
DAQ
IDLE MODE
Chip 2
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 3
Acquisition
A/D conv.
IDLE
IDLE MODE
Chip 4
Acquisition
A/D conv.
IDLE
DAQ
IDLE MODE
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
199ms (99%)
99% duty cycle
1% duty cycle
31 may 2007
C. de La Taille front-end electronics for CALICE

13. HaRDROC chip for DHCAL [LAL,IPNL]
Hadronic Rpc Detector Read Out Chip (Sept 06)
64 inputs, preamp + shaper+ 2 discris + memory + Full power pulsing
Compatible with 1st and 2nd generation DAQ : only 1 digital data output
Discris
Digital
memory 64
Analog
Channels
Dual DAC
Bandgap
Control signals and power supplies
31 may 2007
C. de La Taille front-end electronics for CALICE

14. C. de La Taille front-end electronics for CALICE
HaRDROC architecture
Full power pulsing
Digital memory: Data saved during bunch train.
Only one serial 1 or 5MHz or more
Store all channels and BCID for every hit. Depth = 128 bits
Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits
Based on MAROC ASIC, but several design changes
31 may 2007
C. de La Taille front-end electronics for CALICE

15. C. de La Taille front-end electronics for CALICE
HARDROC: digital part
31 may 2007
C. de La Taille front-end electronics for CALICE

16. HARDROC1: TESTBOARD with Chip On Board
PCB for COB: to estimate feasability (ECAL)
6 layers, COB on Layer 5
2 steps to facilitate the bonding
31 may 2007
C. de La Taille front-end electronics for CALICE

17. C. de La Taille front-end electronics for CALICE
Performance
Good performance
Power dissipation : 1.4mW/channel (unpulsed)
Power pulsing tests starting. Anticipate
S-curves
Good sensitivity to 100fC. Can go down to 10fC
31 may 2007
C. de La Taille front-end electronics for CALICE

18. MEMORY FRAMES: Auto trigger mode
Auto trigger with 10fC:
Qinj=10fC in Ch7
DAC0 and DAC1=255 (~5fC)
Ch7
BCID
Header
31 may 2007
C. de La Taille front-end electronics for CALICE

19. C. de La Taille front-end electronics for CALICE
SKIROC for W-Si ECAL
Silicon Kalorimeter Integrated Read Out Chip (Nov 06)
36 channels with 16 bits Preamp + bi-gain shaper + autotrigger + analog memory + Wilkinson ADC
Digital part outside in a FPGA for lack of time and increased flexibility
Technology SiGe 0.35µm AMS. Chip received may 07, tests starting
31 may 2007
C. de La Taille front-end electronics for CALICE

20. One channel 20M 1M 200ns G=10 G=1 Analog Memory Depth = 5 G=100 G=5
12 bits
ADC
Gain selection
0=>6pF
3-bit threshold adjustment
10-bit DAC
Common to the 36Channels T
100ns
DAC output Q
HOLD
Preamp
Ampli
Slow Shaper
Fast Shaper
Trigger
Charge measurement
3pF
Calibration input
input
31 may 2007
C. de La Taille front-end electronics for CALICE

21. C. de La Taille front-end electronics for CALICE
SPIROC overview
Silicon Photomultiplier Integrated Read Out Chip
A-HCAL read out
Silicon PM detector
G = 3 E5 to 1 E6
Same biasing scheme as TB
36 channels
Charge measurement (15bits)
Time measurement (< 1ns)
Compatible with old & new DAQ
Many SKIROC, HARDROC, and MAROC features re-used
Submission foreseen june 11th
31 may 2007
C. de La Taille front-end electronics for CALICE

22. SPIROC: One channel schematicns
50-100ns
Gain selection
4-bit threshold adjustment
10bit DAC T
15ns
DAC output Q
HOLD
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
Fast ramp 300ns
12-bit Wilkinson
ADC
Trigger
Depth 16
Common to the 36 channels
8-bit DAC
0-5V
Low gain Preamplifier
High gain Preamplifier
Analog memory
50pF
5pF
0.1pF-1.5pF
Conversion 80 µs
READ
Variable delay IN
IN test
Discri
31 may 2007
C. de La Taille front-end electronics for CALICE

23. Acquisition Channel 0 Conversion ADC + readout Ecriture RAM Channel 1
ValidHoldAnalogb 16
RazRangN
Chipsat 16
ReadMesureb 16
Acquisition
NoTrig
gain
Trigger discri Output
Wilkinson ADC Discri output
ExtSigmaTM (OR36)
StartAcqt
SlowClock
Hit channel register 16 x 36 x 1 bits
TM (Discri trigger) 36
BCID 16 x 8 bits
Channel 0
gain
Trigger discri Output
Wilkinson ADC Discri output
Conversion ADC +
Ecriture RAM
StartConvDAQb 36
ValGain (low gain or high Gain)
TransmitOn
readout
RamFull
OutSerie 36
EndReadOut
EndRamp (Discri ADC Wilkinson)
StartReadOut
FlagTDC
Rstb
Channel 1
Clk40MHz
..…
ADC ramp
Startrampb (wilkinson ramp)
RAM
OR36 …
StartRampTDC
TDC ramp
ChipID
Chip ID register 8 bits 8
ValDimGray
DAQ
ASIC
ValDimGray 12 bits 12

24. C. de La Taille front-end electronics for CALICE
On-going R&D : ADCs
Performance (measured):
Resolution: 10 bits
Consumption: 35 mW
Conversion time: 0.25 µs 40MHz)
Integrated cons.: (35mW * 0.25µs)/200ms= .044µW
Characteristics:
Technology: CMOS SiGe 0.35µm
Power supply: 5V (digital: 2.5V)
Clock frequency: 40 MHz
Differential architecture
10 stages bit/stage
Die area: 1.2 mm2
Noise (measured):
< % C.L.
+0.85
-0.70
Integral NL
LSB
Differential NL
+0.56
-0.46
LSB
est-ce que la conso tient compte du power pulsing ou non ??
31 may 2007
C. de La Taille front-end electronics for CALICE

25. C. de La Taille front-end electronics for CALICE
Conclusion
Several large dynamic range ASICs developped for CALICE physics prototypes
ECAL W-Si calorimeter : FLC_PHY3 = 104 channels in beam, dynamic range MIPS
AHCAL Tile-SiPM calorimeter : FLC_SiPM = 103 channels installed, beam in summer 06
DHCAL GEM/RPC
3 major second generation ASICs for technological prototypes submitted
HARdROC submitted for DHCAL RPCs
SKIROC submitted for ECAL Si-W
SPIROC for AHCAL SiPM
Power pulsing, Zero-suppress, Auto-trigger, 2nd generation DAQ…
System aspects not to be forgotten
Power supplies ! Mechanics, reliability…
31 may 2007
C. de La Taille front-end electronics for CALICE

26. C. de La Taille front-end electronics for CALICE
Next steps
Complete physics prototype
Add and test DHCAL, complete physics program
Test effect of em shower on ASIC
Measure performance of 2nd generation ASIC
On testbench in different labs
DHCAL ECAL, AHCAL
Test 2nd generation DAQ (UK)
Design Very Front-End boards with integrated ASICs
ECAL board with FLC_PHY4
DHCAL board with HARDROC
Design EUDET module(s) (demonstrator)
Finalizing Si detectors is now in the critical path (dimensions, layout, AC/DC)
31 may 2007
C. de La Taille front-end electronics for CALICE