1. Scintillator HCAL readout
Felix Sefkow
EUDET / CALICE
electronics meeting
CERN, March 23, 2007

2. Scintillator HCAL readout
Topics:
Scintillator HCAL plans
SiPM and MPPC signals
Noise level requirements
Rate and dead time issues
Trigger timing
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

3. Scintillator HCAL readout
ScHCAL goals
Technology: scalable prototype with integrated electronics and minimized gap
Scintillator sensor PCB integration
Stitchable boards with readout traces
Simplified calibration system
Power and bias management
Combine many
HBUs to layer-
units for assembly.
2000 channels / layer
~ 60 VFE ASICs
~1 FE FPGA
Layer Concentrator (Signals / Power)
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

4. Scintillator HCAL readout
ScHCAL plans
R&D steps
Component prototypes of the above
Thorough study of VFE interplay with SiPM and MPPC
Winter 2007/08
Need VFE test board
FE (VFE DAQ interface) adaptation
Electronics: control software
Build VFE + FE test board (fall 2007?)
Need DAQ prototype: ODR, firmware, software framework
System integration:
power, calibration, monitoring systems
Mechanics: adapt to scintillator cassettes, r/o boards, stack
2008
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

5. Scintillator HCAL readout
ScHCAL physics
Use time measurements to tag neutron hits
Clean up picture for PFLOW reconstruction  cut at 5 ns
Keep late hits for energy resolution  gate open for full bx
T.Takeshita
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

6. Scintillator HCAL readout
Showers with timing
Effect is stronger for Pb
GLD DOD
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

7. Scintillator HCAL readout
Physics plan
Timing measurement is considerable effort
Case must be tested with beam
Can we believe the neutron simulations?
Large differences between models
Can be done with existing HCAL modules
Maybe partial instrumentation sufficient (10 layers, 2k channels)
If SPIROC-1 successful, can be done in 2008
Probably easier with new DAQ than with CRCs
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

8. Scintillator HCAL readout
SiPMs
Critical parameter for SiPM performance is noise above ½MIP threshold
Occupancy < 10-4 translates into rate < ~ 300Hz
Depends on dark rate, inter-pixel crosstalk and light yield; Rule of thumb: N(T) = Ndark * (Xtalk)T=LY/2
E.g. 2 MHz * (0.3)7 = 400 Hz
Presently up to 3 kHz
Light yield determines dynamic range and MIP efficiency
Minimum 7-10 pixels/MIP - If threshold at 1.5 px possible
Will always set threshold as low as possible
To maximize MIP efficiency, energy resolution and robustness
Electronics noise must not be limiting factor
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

9. Scintillator HCAL readout
Misha Danilov
Comparison of different Multipixel Geiger Photo Diods (MGPD)
MGPD were illuminated with
Y11 (green) and
scintillator (blue) light
Efficiency was normalized
to MPPC one .
Noise frequency
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

10. SPIROC: One channel schematicns
50-100ns
Gain selection
8-bit threshold adjustment
Reference voltage T
15ns
DAC output Q
HOLD
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
Fast ramp 300ns
12-bit Wilkinson
ADC
Trigger
Depth 16
Common to the 36 channels
8-bit DAC
0-5V
Low gain Preamplifier
High gain Preamplifier
Analog memory
50pF
5pF
0.1pF-1.5pF
Conversion 80 µs
READ
Variable delay IN
IN test
Discri
Ludovic Raux
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

11. SPIROC : Photoelectron response simulation
Ludovic Raux
Simulation obtained with SiPM gain = _ 1 pe = 160 fC
High gain Preamplifier response
Low gain Preamplifier response
Fast shaper
Tp=15ns
Noise/pe ratio = 25
120mV/pe
High gain Slow shaper
10mV/pe
Tp=50ns
Noise/pe ratio = 11
Low gain Slow shaper
Tp=50ns
1mV/pe
Noise/pe ratio = 3
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

12. Scintillator HCAL readout
Noise limits
Gain can be as small as 0.2*106
Noise can be so low that threshold at 1.5 p.e is possible
Trigger mode:
limit given by occupancy: 10-4  T > 4-5 σ( Noise)
Noise must be below 1/5 * 1.5 * 0.2 * 106 e  N/p.e.> 17 
High gain mode:
Limit given by separation of single p.e. peaks  G > 3-4 σ (Noise)
Noise must be below 1/4 * 0.2 * 106 e  N / p.e. > 20 
Low gain mode:
Limit given by MIP resolution dominated by Poisson statistics: σ(Noise) < 1/3 σ( Poisson)
Noise must be below 0.2 * 106 e  N / p.e > 5 
High gain (“calibration”) mode most challenging
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

13. Scintillator HCAL readout
Experience with MPPCs
Operated at 2.something V  gain * 106 (~ SiPM)
Just works
Keep an eye on dynamic range
Actually no saturation seen so far in DESY 6 GeV e beam
N oise= 40 ADC
(calib mode)
B.Lutz
MPPC noise
Satoru Uozumi
Gain = 150 ADC
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

14. Scintillator HCAL readout
subjects of study
Benjamin Lutz
response for real signals: Is output signal amplitude linearly proportional to input signal charge?
What differences do we expect for different photo sensors?
auto-trigger: What is the expected difference to nowadays trigger generation?
Does this avoid jitter problems with short shaping time?
What do we expect in the single photon detection mode?
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

15. Scintillator HCAL readout
input signal *
ASIC response =
output signal
Benjamin Lutz = * =
scope measurement
(DESY)
simulation
(LAL) =
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

16. singel photon detection
5 shots of one light intensity setting
slow shaping
auto
trigger
To be
simulated
fast shaping
Benjamin Lutz
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

17. Scintillator HCAL readout
Data volume
ECAL: SKIROC
968 bits per time slice and 72 channels
Buffer depth 5  5 kbit / chip
Slab
7200 channels  100 VFE / FE
If RAM full: 500 kbit / FE
Occupancy
Data reduction: JC 10-4, MW 10-2
10-4: per event: 10k hits or (50cm)2 or (10cm)2 in 25 layers
2000 hits per slab and train
Distribution
ILC: non-uniform per event, random and largely uniform per train
Test beam: non-uniform and constant, up to 1
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

18. Scintillator HCAL readout
FE readout speed
Power considerations
Assume bus capacitance 500 pF, gives I=1 MHz x 500 pF x 2V = 1mA
Power dissipation 10 µW / chip, 1 mW for 100 chips
 Readout clock speed few MHz: MHz
Might not be a hard limit – only # of bit flips count
Daisy-chain VFEs: assume serial readout here
Note: parallel lines to FE  shorter r/o times
ECAL: read 100 SKIROCS with 100 x 5 kbit
At 5 MHz: 100 ms
(At 1 MHz: 500 ms  too slow for ILC)
ILC: fine above 2.5 MHz
Fewer VFE / FE: cost prohibitive (~300 € / FE)
Test beam: asymptotic rate 5 events per cycle = 50 Hz (10 Hz)
Can be higher if smaller number for VFEs read
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

19. Scintillator HCAL readout
ECAL buffer depth: ILC
ILC: 3 MHz for 1 ms
Occupancy 10-4 implies 300 Hz per channel, 0.3 hits per train
 No problem for individual channel trigger
.OR.ed trigger for 72 channels: 22 kHz, 22 triggers per train
 Need additional assumptions to justify buffer depth of 5
Concentrated showers: concentrate 22 hits in < 5 time slices
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

20. ECAL buffer depth: test beam
Testbeam: 1-10 kHz for several seconds
Occupancy 1 in central beam impact region
5 buffers full after 0.5 – 5 ms
kHz is max rate for ILC-like spill structure
5 MHz readout: 100 ms: >95% dead time, 50 Hz asymptotic rate
10 Hz for 1 MHz r/o
20x20 cm2: 1600 channels, 20 chips , 250 (50) Hz asymptotic
With 10% duty cycle of the beam marginally acceptable
Multi-chip read-out in test beam: only technical test
10 % duty cycle of spill: 1-5 Hz average rate
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

21. Scintillator HCAL readout
SiPM readout
SPIROC: Data volume:
36 channels, ADC + TDC (+ time stamp(s)) = 876 (1296) bits / event
16 time slices: 14 kbit (20.7kbit)
Readout speed:
5 MHz: 3-4 ms / chip if RAM full
1 MHz: ms / chip
ILC: 200 ms max readout time
5 MHz: max 50 VFE / FE, 1 MHz: max 10 VFE / FE (or parallel)
HCAL layer 2000 channels / 36/chip = 60 chips  < 5 MHz: > 1 FE
Test beam:
Asymptotic rate: 16 / ms = Hz
Test beam layer: 1 m2  only 2x faster
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

22. Scintillator HCAL readout
SiPM occupancy
Physics hits: in ttbar events # HCAL (3x3) ~ 1/3 # ECAL (1x1)
Total # channels 5M vs 24 M here: occupancy about the same
Background hits: need to re-evaluate, probably < ECAL
Noise: rates above threshold in physics mode:
Presently up to 3 kHz
Ultimate requirement driven by occupancy considerations
10-4 translates into 300 Hz, see ECAL case
Granularity 40x smaller than ECAL: no band width issue
Accepting only prompt signals in short gate of ns wins factor 3-6  can accept up to 2 MHz, but no late hits then
Low thresholds needed for low light intensity / thin scintillator
 Occupancy characterized by noise, large uniform component
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

23. SiPM buffer depth: ILC case
ILC mode: 3 MHz
300 Hz – 3 kHz noise: 0.3 to 3 hits per train
Buffer depth of 16 ok for individual trigger
.OR. of 36 channels: trigger rate of 10 – 100 kHz
Buffer of 16 slices fills up in 0.16 – 1.6 ms
Not sufficient for ILC cycle
Independent of physics topology, because noise and not physics induced
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

24. SiPM buffer depth: test beam
Testbeam mode
Need to adjust readout cycle to noise rate and buffer depth
Shorten r/o cycle to 0.1 ms?
Asymptotic rate stays the same: 80 Hz for 200 ms r/o
BUT:
Without external trigger read mainly noise
Physics fraction = beam rate / noise rate ~ 1/10 … 1/100
Effective rate for 1 kHz beam
only 1 or few Hz for .OR.ed auto-trigger
Order of 50 Hz for individual trigger
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

25. Scintillator HCAL readout
Fast timing 1
In present system shaping acts as latency – and is too short
Would like to go from 200 ns to, say, 400 ns
SiPM shaping in physics mode is shorter ( ns)
 need to decouple shaping and latency, store charge in-between
See next slide
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

26. Scintillator HCAL readout
SPIROC timing, naively
sample
hold
reset
10ns
50 ns
300 ns
400 ns
stop
TDC
External trigger
Or beam clock
start
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

27. Timing, more realistically
validate
hold
reset
10ns
50 ns
300 ns
5000 ns
drive
TDC
External trigger
stop
start
beam clock
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

28. Scintillator HCAL readout
Fast timing 2
If validation in next clock cycle, loose data
Dead-time = latency / clock (in test beam only)
Long cycle (50000 ns): < 10%, no problem
Hold in next cycle: to be clarified
Promising solutions underway – do they co-exist with ECAL and DAQ?
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout

29. Scintillator HCAL readout
Conclusion
There is physics in the new EUDET chips
We rely on modular DAQ and FE hardware and software
The SPIROC analogue front end is challenged by low gain low noise MPPCs
For SiPM readout, occupancy will be dominated by noise
ILC will need full channel-by-channel zero suppression
Test beam with ORed auto-trigger and limited buffer depth needs external trigger validation
Fast timing is tricky…
Felix Sefkow CALICE / EUDET electronics
Scintillator HCAL readout