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27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice Electromagnetic Calorimeter.

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Presentation on theme: "27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice Electromagnetic Calorimeter."— Presentation transcript:

1 27 th May 2004Daniel Bowerman1 Dan Bowerman Imperial College 27 th May 2004 Status of the Calice Electromagnetic Calorimeter

2 27 th May 2004Daniel Bowerman2 Prototype Overview 62 mm 200mm 360mm 30 layers of variable thickness Tungsten Active silicon layers interleved Front end chip and readout on PCB board Signals sent to DAQ Tungsten layers wrapped in Carbon Fibre 8.5 mm for PCB & Silicon layer 6x6 1x1cm 2 silicon pads Connected to PCB with conductive glue PCB contains VFE electronics 14 layers, 2.1mm thick Analogue signals sent to DAQ

3 27 th May 2004Daniel Bowerman3 Silicon Wafers 62 mm 4” High resistive wafer : 5 K  cm Thickness : 525 microns  3 % Tile side : 62.0 mm including Guard ring In Silicon ~80 e-h pairs / micron  42000 e - /MiP Capacitance : ~21 pF Leakage current : 5 – 20 nA Full depletion bias : ~150 V Nominal operating bias : 250 V Each Wafer: Matrix of 6 x 6 pixel of 1 cm 2 Require 270 active wafers for the Prototype 150 to be produced by Institute of Nuclear Physics – Moscow State University First test production: February 2003, 130 wafers produced already 150 to be produced by Institute of Physics, Academy of Sciences of Czech Republic,Prague First test production: March 2004, 15 produced already, full production by end of June Both sets of Wafers are of high quality

4 27 th May 2004Daniel Bowerman4 Very Front End Electronics Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel Preamp with 16 gains (gain selected offline) CR-RC shaper (~200ns), track and hold 18 channels in, one Multiplexed output Each chip serves 18 channels, 2 chips per wafer Linearity: ± 0.2 % Range: ~600 MIPS Crosstalk < 0.2% 3 generations of improving production Numbers quoted refer to V2 V3 produced, and being tested VFE consists of

5 27 th May 2004Daniel Bowerman5 Production & Testing Mounting/gluing the wafers Using a frame of tungsten wires 6 active silicon wafers 12 VFE chips 2 calibration switch chips Line Buffers To DAQ PCB designed in LAL-Orsay, made in Korea (KNU) 60 Required for Prototype, ready in July An automatic device is use to deposit the conductive glue : EPO-TEK® EE129-4 Gluing and placement (  0.1 mm) of 270 wafers with 6×6 pads, 10 000 points of glue About 10 000 points of glue. Production line set up at LLR

6 27 th May 2004Daniel Bowerman6 Production & Testing Must validate assembly, mounting and performance of each PCB Dedicated DAQ system to test individual PCBs Use in conjunction with Cosmic test bench, or 90 Sr β decay Scintillator Plane Scintillator Plane VFE- PCB Daq board and control signals to VFE PCB Interconexion Panel Trigger generator

7 27 th May 2004Daniel Bowerman7 First tests with prototype PCB Sr 90 source  trigger  read 6 channels Only ONE with signal 5  Noise MIP output ADC Noise “external” signal -Theoretic result: 4.97mV -Measured : 5.05mV -Theoretic result: 4.97mV -Measured : 5.05mV 1 MIP injected in channel 10 with Calibration chip and measurement made on 100 points “internal” signal

8 27 th May 2004Daniel Bowerman8 Prototype DAQ Use custom VME readout board Based on CMS tracker front-end board (FED) Uses several FPGA’s for main controls Dual 16-bit ADCs (500 kHz) and 16-bit DAC On-board buffer memory 8 Mbytes. 1.6k event buffer, no data reduction Prototype design completed last summer Two prototype boards fabricated in November Noise ~ 1ADC count Linear to 0.01% Gains uniform to 1% Further tests, final production ~ July

9 27 th May 2004Daniel Bowerman9 Full Chain - Cosmics Now attach PCB to Prototype DAQ board – Full Detector Chain Use track interpolation from scintillators to select events Clear cosmic MIP peak seen, ~45 ADC counts above pedestal MIP = 200 keV; calibrates ADC so 1 count = 4.4 keV 32k full range ~ 700 MIPs; requirement > 600 MIPs Noise per channel ~ 9 ADC counts = 40 keV MIP:noise ~ 5:1; requirement > 4:1 Expect 7.5:1 from initial tests with new VFE chip Selecting events with at least one pad > 40 ADC counts (4σ cut) Clearly highlights the active 6  6 cm 2 silicon wafer Can survey wafer positions, and cross-check readout positions

10 27 th May 2004Daniel Bowerman10 Full Chain - Cosmics Example of Cosmic Event Passes through scintillators Extrapolated through silicon Appears as clear signal above background Scintillator Wafer X-Z plane Y-Z plane

11 27 th May 2004Daniel Bowerman11 Future Technology R&D Prototype design is not realistic as: - Industry cannot build 1.6 m PCB; tendancy is for smaller PCBs -High line capacitance  very noisy -Large number of lines  crosstalk issue and many PCB layers R&D for the full scale detector is also progressing Possible solution: VFE Chip mounted near wafers -1 chip per wafer -Low power issue -Cooling issues -Temperature distribution in module? -Fake signal due to e.m. showers in chip Simulation Thermal dissipation with internal cooling at the border with liquid flow Two chips produced this year, simulation underway, cooling prototype and test bench being developed. Future DAQ ideas also being investigated Big Issue: Funding mechanism for this R&D not established

12 27 th May 2004Daniel Bowerman12 Prototype Status and Timelines Prototype components status: All elements of the prototype are at or are close to schedule All wafers/PCB’s tested by October 2004 Plan for low energy electron test beam at DESY before the end of the year High energy electron/hadron test beams with HCAL at FNAL/IHEP next year

13 27 th May 2004Daniel Bowerman13 Conclusions Great deal of progress in the past 18 months All prototype components in production and at or close to schedule Performance of individual components at or better than required Complete detector chain in place and tested Captured Cosmics and β decays Good Signal to Noise Extensive testing to ensure quality of prototype components Preparing for Test Beam at DESY by the end of the year Full ECAL & HCAL hadron test beam next year

14 27 th May 2004Daniel Bowerman14 Ecal concept e + e –  ZH, Z   at  s=500 GeV HCAL COIL ECAL Jet Energy resolution is key to LC detector performance Energy Flow technique gives best Jet Energy resolution Requires tracking calorimetry to resolve individual particles Tracking Calorimeter requires high granularity/segmentation Ecal : Si-W sampling calorimeter, 40 layers, 1x1 cm 2 pads, 32 M channels, 24X 0 in 20 cm Require Testbeam – Monte Carlo tuning to accurately determine possible jet resolution

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