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AIDA KICK OFF MEETING WP9

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Presentation on theme: "AIDA KICK OFF MEETING WP9"— Presentation transcript:

1 AIDA KICK OFF MEETING WP9
AIDA KICK OFF MEETING WP9.5: FEE sub-task Nathalie Seguin-Moreau Gisèle Martin-Chassard

2 Second generation ASICs for EUDET
Auto-trigger, analog storage, digitization and token-ring readout Power pulsing : <1 % duty cycle Optimize commonalities within EUDET (readout, DAQ…) Dedicated run produced in March 2010 25 wafers received in June chips packaged in the US HARDROC2 SDHCAL RPC 64 ch 20 mm2 SKIROC2 ECAL Si 64 ch. 65 mm2 SPIROC2 AHCAL SiPM 36 ch 32 mm2 FLC_PHY3 (2003) AIDA Kick Off meeting: WP9.5 FEE

3 HaRDROC : ILC (RPC) DHCAL readout
Hadronic Rpc Detector Read Out Chip 64 inputs, preamp + shaper+ 3 discris Full power pulsing => 7 µW/ch Fully integrated ILC sequential readout Chip embedded in detector chips produced in March to equip ch HARDROC2B: run 2009 20 mm2= 20 k€ Fully equipped scalable m2 RPC SDHCAL detector built by IPN Lyon F. Dulucq, G. Martin-Chassard, N. Seguin-Moreau AIDA Kick Off meeting: WP9.5 FEE

4 SPIROC : ILC AHCAL readout
SPIROC : Silicon Photomultiplier Integrated Readout Chip 36 channels Internal 12 bit ADC/TDC Charge measurement (0-300 pC) Time measurement (1 ns) Autotrigger on MIP or spe (150 fC) Sparsified readout compatible with EUDET 2nd generation DAQ Pulsed power -> 25 µW/ch (0.36m)2 Tiles + SiPM + SPIROC (144ch) pedestal MPV of MIP distribution ©E. Garutti (DESY) 32 mm2 32 k€ S. Callier, F. Dulucq, J. Fleury, L. Raux AIDA Kick Off meeting: WP9.5 FEE

5 AIDA Kick Off meeting: WP9.5 FEE
SKIROC : ECAL readout SKIROC2 : Silicon Kalorimeter Integrated Read-Out Chip 64 channels, 65 mm2 Very large dynamic range: HG for MIP LG for Mip Internal 12 bit ADC/TDC Time measurement (< 1 ns) Autotrigger on MIP (4 fC) Sparsified readout compatible with EUDET 2nd generation DAQ Pulsed power -> 25 µW/ch Testability at wafer level 65 mm2 => 65 k€ S. Callier, F. Dulucq, N. Seguin-Moreau AIDA Kick Off meeting: WP9.5 FEE

6 WP9.5: electronics readout
1st year: Characterization of the 2nd generation ROC chips Testbench/testbeam measurements Prototyping of the 3rd generation of ROC chips. Main modifications: New Slow Control with I2C link For all the ROC chips New digital part: Independent channels (all chips ?) Read-Out, BCID management New TDC (step=1 ns, no dead time): For SKIROC3 and SPIROC3 New SCA: For SPIROC3 and SKIROC3 Circular memory for HARDROC3 ? Analog part Preamp modifications for SPIROC3 HARDROC2 SDHCAL RPC 64 ch 20 mm2 SKIROC2 ECAL Si 64 ch. 65 mm2 SPIROC2 AHCAL SiPM 36 ch 32 mm2 AIDA Kick Off meeting: WP9.5 FEE

7 AIDA Kick Off meeting: WP9.5 FEE
Design difficulties ASIC: design/simulation/layout : 12 ppm New SCA + new TDC: 6 ppm, areax2 I2C interface : slave already designed and tested by IPNL 8 extra pads for address Serial interface but // distribution inside the chip 500 to 1000 SC parameters/chip => 500 to 1000 wires inside the chip Independent channels : HR3 : 6 ppm + Area x 1.3 Decrease nb of events stored (127/chip  8/ch) New custom RAM per ch (+ 6 ppm or + 6K€) SP3 : new architecture, 12 ppm + Area x 1.5 Decrease depth of SCA (16  8) AIDA Kick Off meeting: WP9.5 FEE

8 MILESTONES and SCHEDULE
Milestones: Report in 30 months (August 2013) AIDA budget for 3rd generation of electronics: 78 k€ (equipment) => 2 chip submissions (Hardroc3 and Spiroc3) 30 ppm Cost: Multi Project runs (MPW): 1k€/mm2 Packaging: $3500 Test-board: 1500 € Schedule 1st chip : SPIROC3 Submission March 2012 Reception June 2012 1 year for tests and report 2nd chip : HARDROC3 Submission March 2013 Reception June 2013 1 year for tests HARDROC2 SDHCAL RPC 64 ch 20 mm2 SKIROC2 ECAL Si 64 ch. 65 mm2 SPIROC2 AHCAL SiPM 36 ch 32 mm2 AIDA Kick Off meeting: WP9.5 FEE

9 AIDA Kick Off meeting: WP9.5 FEE
Backup slides AIDA Kick Off meeting: WP9.5 FEE

10 Multi Project Run vs Dedicated Run
MPW: 1k€/mm2 25 dies delivered, to be packaged Hundreds of dies are usually available (no guaranty): about 100 euros/die Packaging: ~ $3.500 HR2 20 mm2: 20 k€, SKIROC2 65 mm2: 65 k€ SPIROC2 32 mm2: 32k€ Engineering run: Wafer 8’’, thinned down to 250 µm 2nd generation chip production: 250 k€ Thinning, Dicing, Packaging: 40 k€ AIDA Kick Off meeting: WP9.5 FEE


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