1. HARDROC HAdronic Rpc ReadOut Chip
IN2P3/LAL+IPNL+LLR R. GAGLIONE, I. LAKTINEH, H. MATHEZ (IN2P3/IPNL LYON) M. BOUCHEL, J. FLEURY, C. de LA TAILLE, G. MARTIN-CHASSARD, N. SEGUIN-MOREAU (IN2P3/LAL ORSAY) V. BOUDRY, J.C. BRIENT, C. JAUFFRET (IN2P3/LLR PALAISEAU)

2. Digital calorimetry in ILC
Particle Flow Algorithm requires high longitudinal and transverse granularity in calorimetry for precise jet measurement
It implies highly segmented steel sandwich hadron calorimeter (HCAL)
Digital Hadron Calorimeter (DHCAL) may provide fine segmentation (~1cm2) with simplest yes/no read out system which is enough for neutral hadron pattern recognition and muon ID
Train length bunch X (950 us)
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns
IMAGING CALORIMETRY
ILC BEAM
3-9 sept 07
HARDROC TWEP PRAGUE

3. DHCAL: Concept of a Digital Hadronic CALorimeter
Absorber: 40 steel plates of 20 mm (~1X0), corresponds to 4λ
Active medium: Resistive plate chambers (RPC) or GEM or MICROMEGAS.
High granularity : 1x1 cm2
High segmentation => channels for the entire HCAL
2bit resolution per PADs to preserve single particle resolution
FE Chip embedded inside the detector
Reduction of the power consumption to 10uW/channel (power pulsing possible thanks to ILC bunch pattern)
Train length bunch X (950 us)
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns
ILC BEAM
3-9 sept 07
HARDROC TWEP PRAGUE

4. HARDROC ASIC: main requirements
Full power pulsing
64 inputs (low Zin), 1 serial output
1 variable gain preamp/channel with 6 bits accuracy (G=0 to 4 with 6% accuracy)
Multiplex analog charge output (debugging)
Variable gain fast shaper (15 ns) and 2 low offset discriminators: autotrig on 10fC
Thresholds loaded by 2 internal 10bit-DACS
A 128 depth digital memory: 20k data transferred during interbunch
ASICS embedded inside the detector for compactness and daisy chained to minimize output lines on the detector
Analog and digital crosstalk to be minimised
1700 chips to be produced in 2007 for a 1m3 DHCAL prototype
3-9 sept 07
HARDROC TWEP PRAGUE

5. HaRDROC architecture Only one serial output @ 1 or 5MHz
Full power pulsing
Digital memory: Data saved during bunch train.
Only one serial 1 or 5MHz
Store all channels and BCID for every hit. Depth = 128 bits
Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits
Based on MAROC ASIC, but several design changes
3-9 sept 07
HARDROC TWEP PRAGUE

6. HARDROC1: TESTBOARD with Chip On Board
PCB for COB:
6 layers, Chip on Layer 5
2 steps to facilitate the bonding
3-9 sept 07
HARDROC TWEP PRAGUE

7. Trigger efficiency: Scurves (1)
Charge injected in one channel: 100fC
Typically 3.5mV/fC
Scurves performed by varying the DAC value (Threshold)
2 integrated DACs to deliver Threshold voltages
Residuals within ±5 mV / 2.6V dynamic range. INL= 0.2% (2LSB)
2.5 mV/DAC Unit ie 0.7 fC/UADC
Out
DC=2V
350 mV
3-9 sept 07
HARDROC TWEP PRAGUE

8. Trigger efficiency: Scurves
DAC0=Vth0=180 (~2.1V)
Pedestal (Qinj=0)
DC=2V
Qinj=100fC
Vth0=350 (~1.65V)
240
Pedestal
Trigger
Efficiency
Vth0
3-9 sept 07
HARDROC TWEP PRAGUE

9. Scurves of the 64 channels, Gain PA=1
Charge injected in each channel: 100fC
Non uniformity quite large (±25%) due to current mirror mismatch (small transistors to optimise speed)
Can be compensated by tuning the gain of each channel (measurement to be redone).
3-9 sept 07
HARDROC TWEP PRAGUE

10. Scurves of the 64 channels, Gain PA=1
After tuning the gain of each channel
3-9 sept 07
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11. Scurves of the 64 channels, Gain PA=1
After tuning the gain of each channel
3-9 sept 07
HARDROC TWEP PRAGUE

12. FSB DC measurement: Uniformity
3-9 sept 07
HARDROC TWEP PRAGUE

13. SS waveforms (scope measurements)
Out Q: Very usefull for detector characterisation
Compatible with existing DAQ0 used on testbeam
SS: 10 pC => 535mV, slowest peaking time:tp=150 ns
Slow Shaper (SS)
10 pC
1pC
DC level
≈ 1V
3-9 sept 07
HARDROC TWEP PRAGUE

14. Zin and Xtk Zin (PA)=50Ω with Vgain=3V, Zin (PA)=70Ω with Vgain=3.5V
Qinj=100fC on Ch7
out_fsb=160mV (on 50Ω), tp=15ns
Xtk: well differentiated
Ch6: ± 3mV
Ch8: ± 3mV (± 2%)
Ch9: ± 0.5mV
Xtk: on the input
Gain=1 on Ch7 and Gain=0 on Ch8,
=> Xth (ch8)=0
Ch7
Xtk Ch8 *100
Discri out/10
Scope, 50Ω)
3-9 sept 07
HARDROC TWEP PRAGUE

15. Trigger Xtk: DAC0 and DAC1= 300 (=> Vth0 =Vth1~50fC) Qinj in Ch7
Up to 1.6 pC: triggers on CH7 only, nothing on the neighbors
1.8 pC: Triggers on Ch7 and CH6, no trig on other channels
2 pC up to 5,6pC: Triggers on CH7, CH6 and 8
10pC Triggers on Ch7 and on the 4 direct neighbors.
Ch7
Ch6
Ch8
1.8pC
50fC
3-9 sept 07
HARDROC TWEP PRAGUE

16. FPGA Config/Clock Extract
Digital part (1)
Chips to be embedded and daisy chained to minimise number of output lines inside the detector
VFE ASIC
Data
ADC
I/O
Buffer
FE-FPGA
BOOT CONFIG
Data Format
Zero Suppress
Protocol/SerDes
FPGA Config/Clock Extract
Clock
Bunch/Train Timing
Config Data
Clk
Slab FE
FPGA
PHY
Clock+Config+Control
VFE
ASIC
Conf/
RamFull
Analog output
DIF
USB
SCS I
3-9 sept 07
HARDROC TWEP PRAGUE

17. Digital part: DAQ2 DHCAL DAQ and online system Common to all detectors
Crateless, non-custom, ILC-like system with readout directly into PCs
System-dependences isolated to single interface (LDA-DIF)
Offline software
Common and based on LCIO, Grid
3-9 sept 07
HARDROC TWEP PRAGUE

18. MEMORY FRAMES: Auto trigger mode
Auto trigger with 10fC:
Qinj=10fC in Ch7
DAC0 and DAC1=255 (~5fC)
Ch7
BCID
Header
3-9 sept 07
HARDROC TWEP PRAGUE

19. Power dissipation Measured power dissipation (no power pulsing)
Preamp : 6 mA = 100 µA/ch
Fast shaper : 5,3 mA
Discriminators (2) : 5.9 mA
Slow shaper (used only for backup) : 14.5 mA
DAC : 0.8 mA
Bandgap reference : 5 mA
Digital part : 3 mA
Total : : 26 mA*3.5V = 90 mW/64ch = 1.4 mW/channel
140 mW if slow shaper (analog readout) is used
Need to test power pulsing (0.5 to 1% duty cycle) -> 8-15 µW/ch
3-9 sept 07
HARDROC TWEP PRAGUE

20. PCB with 4 HARDROC
First detector with 2nd generation ASCIs and 2nd generation DAQ
8X32 pads detector RPC, 8 layer PCB optimised to reduce Xtk and compatible with µMEGAS detector
Board received in june 07, tests starting
Test beam and cosmics
1 cm2 pads
500 µ separation
3-9 sept 07
HARDROC TWEP PRAGUE

21. HARDROC1 PERFORMANCE SUMMARY
Number of inputs/outputs
64 inputs, 1 serial output
Input Impedance
50-70Ω
Gain Adjustment
0 to 4, 6bits, accuracy 6%
Bipolar Fast Shaper
≈3.5 mV/fC tp=15ns
10 bit-DAC
2.5 mV/fC, INL=0.2%
Trigger sensitivity
Down to 10fC
Slow Shaper (analog readout)
≈50 mV/pC, 5fC to 15pC , tp= 50ns to 150ns
Analog Xtk 2%
Analog Readout speed
5 MHz
Memory depth
128 (20kbits)
Digital readout speed
5MHz or more
Power dissipation (not pulsed)
100 mW (64 channels)
3-9 sept 07
HARDROC TWEP PRAGUE

22. CONCLUSION
3-9 sept 07
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23. ANNEXE
3-9 sept 07
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24. ANALOG PART
3-9 sept 07
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25. HARDROC1: digital part
3-9 sept 07
HARDROC TWEP PRAGUE

26. 8x32 pads: RPC and µMegas RPC
6 PCBs (4chips): received beginning of MAy
Tests with cosmics (standalone USB DAQ) in LLR +IPNL in June
Tests in July07 with test beam at DESY and CERN with DAQ0
Can be used for DAQ2 tests (UK)
8 layer PCB
FPGA
4 areas of 64 pads of 1 sq cm : bottom layer
Hardroc external components : top layer
3-9 sept 07
HARDROC TWEP PRAGUE