1. HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)
IN2P3/LAL+IPNL+LLR R. GAGLIONE, I. LAKTINEH, H. MATHEZ IN2P3/IPNL LYON M. BOUCHEL, R. CHICHE, J. FLEURY, C. de LA TAILLE, G. MARTIN-CHASSARD, N. SEGUIN-MOREAU IN2P3/LAL ORSAY J.C. BRIENT, C. JAUFFRET IN2P3/LLR PALAISEAU

2. HaRDROC architecture Only one serial output @ 5MHz Full power pulsing
Digital memory: Data saved during bunch train.
Only one serial 5MHz
Store all channels and BCID for every hit. Depth = 128 bits
Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits
Based on MAROC ASIC, but several design changes
23 March 07
HARDROC CERN

3. HARDROC1: TESTBOARD with a packaged chip
5 packaged ASICs, 10 naked dies received in january 07
7 testboards
23 March 07
HARDROC CERN

4. HARDROC1: TESTBOARD with Chip On Board
23 March 07
HARDROC CERN

5. SS and BFS waveforms (scope measurements)
DC level
≈ 2V
100fC
Bip. Fast Sh (BFS)
Slow Shaper (SS)
10 pC
BFS: 100fC => 350mV, tp=15ns, ie 3.5mV/fC
SS: 10 pC => 535mV, tp=150 ns
1pC
DC level
≈ 1V
23 March 07
HARDROC CERN

6. DC meas. of FSB and SS: Uniformity
<>=2V, σ=1.3mV
<>=1.10V σ=1.8mV
23 March 07
HARDROC CERN

7. HARDROC1: Integrated DACs linearity
2 integrated DACs to deliver Threshold voltages
Residuals within ±5 mV / 2.6V dynamic range. INL= 0.2% (2LSB)
2.5 mV/UDAC
23 March 07
HARDROC CERN

8. Zin and Xtk Zin (PA)=50Ω with Vgain=3V, Zin (PA)=70Ω with Vgain=3.5V
Qinj=100fC on Ch7
out_fsb=160mV (on 50Ω), tp=15ns
Xtk: well differentiated
Ch6: ± 3mV
Ch8: ± 3mV (± 2%)
Ch9: ± 0.5mV
Xtk: on the input
Gain=1 on Ch7 and Gain=0 on Ch8,
=> Xth (ch8)=0
Ch7
Xtk Ch8 *10
Discri out/10
Scope, 50Ω)
23 March 07
HARDROC CERN

9. Trigger:
Trigger down to 10 fC
Time walk
23 March 07
HARDROC CERN

10. Trigger efficiency: Scurves
Vth0=180 (~2.1V)
Vth0=350 (~1.65V)
DC=2V equivalent
to DAC=240
Pedestal
Pedestal
Trigger
Efficiency
Vth0
23 March 07
HARDROC CERN

11. Scurves, Gain PA=1 and 4 Gain=1 Gain=1 Pedestal Qin=100fC Gain=4
Piedestal
Qin=10fC
Qinj=10fC
23 March 07
HARDROC CERN

12. HARDROC1: digital part
23 March 07
HARDROC CERN

13. HARDROC1: bugs…
23 March 07
HARDROC CERN

14. HARDROC1: first detected bugs…
Not possible to see each output of the 64 RS latches on scope:
the state of the latch is changed when the Read signal is sent to the switch of the channel to be read
Need to add a buffer before the multiplex switch
The valid_trig command (Ch0 to 63) doesn’t work.
Valid trig=0
RazChn=1
ValEvt=1
If out_dicri =0 => out_RS=0
If out_discri=1 => out_RS=1…..
RS_trig out
23 March 07
HARDROC CERN

15. MEMORY FRAMES Dout_007 is displayed on the scope.
CK used for the readout: 1.25MHz
!1st frame: irrelevant
SETUP:
DAC0=800
=>Vth0=660mV
=> RS_trig0=0
DAC1=0
=>Vth1=2.60V
=> RS_trig1=1
2nd frame:
Header (8bits), then BCID (24bits),
then 128 bits for trig0<0-63> and trig1<0-63>
23 March 07
HARDROC CERN

16. MEMORY FRAMES DAC0 and DAC1=0 DAC0 and DAC1=800 DAC0=0 and DAC1=800
23 March 07
HARDROC CERN

17. Digital architecture towards 2nd generation DAQ
ECAL, AHCAL, DHCAL
Slab FE
FPGA
PHY
Data
Clock+Config+Control
VFE
ASIC
Conf/
Clock
detector readout
RamFull
BOOT CONFIG
FE-FPGA
Data Format
Zero Suppress
Protocol/SerDes
FPGA Config/Clock Extract
Clock
Clk
VFE ASIC
Bunch/Train Timing
Config Data
1G/100Mb Ethernet PHY
ADC
Data
23 March 07
HARDROC CERN

18. 8x32 pads: RPC and µMegas RPC - PCB (6) and chambers in March07
8 layer PCB
- PCB (6) and chambers in March07
- Tests in April07 with cosmics
- Tests in July07 with test beam
FPGA
4 areas of 64 pads of 1 sq cm : bottom layer
Hardroc external components : top layer
23 March 07
HARDROC CERN

19. Summary Analog part of hardroc1: ongoing measurements. Digital part:
first frames but still a lot of work
1 testboard already in London (Matt Noy),boards should be available for Protvino, IPN Lyon and LLR soon
Production of 6 DHCAL prototype PCBs
PCB goes to fab this week
Components: should be all delivered at the end of March
Hardroc chips : 70 more bought, need packaging (200 €/chip!)
Manpower for test program and for measurements
23 March 07
HARDROC CERN