1. Electronics for Si-W calorimeter
LCWS06 Bangalore – March, 10th
Gérard Bohner, Pascal Gay, Jacques Lecoq
Samuel Manen, Laurent Royer
Michel Bouchel, Bernard Bouquet, Julien Fleury
Christophe de La Taille, Gisèle Martin, Roman Poeschl

2. General introduction

3. General overview of Si-W calo
CALICE ECAL proposal (LDC) :
Octogonal shape
40 identical structures
Active materials in detector slab
Million channels
Depending on pad size (1cm or .5cm)
Electronic requirement :
Electronic embedded in the slab
Ultra-low power consumption (~100µW/Ch)
To avoid active cooling
Ultra-thin design
To reduce moliere radius
R&D on a technologic prototype as started

4. EUDET framework European funding for ILC detectors
CALICE labs are members of JRA3 (Joint Reasearch Activities for calorimeters)
Part of this funding will be used to build a technologic prototype of ECAL
EUDET is a 4-year funding program
 Technologic prototype is a 2009 deliverable
That technologic prototype has to be as close as possible to final design

5. EUDET : ECAL emodule Electromagnetic calorimeter technologic prototype
Prototype of a (~ 1/6) module 0 : one line & one column
150 cm long, 12 cm wide 30 layers
channels
Test full scale mechanics + PCB
Can go in test beam
Test full integration + edge communications
Similar in #channels as physics prototype
©M. Anduze (LLR)

6. R&D on PCBs

7. Thickness considerations
Chip in the detector
Thickness
Ultra-thin PCB
Chip burried in PCB
1750µm diodes+ FE electronic
PCB (600µm)
FE chip (1mm)
Wafer (500µm)

8. Length considerations
Industry can’t build 1.5m PCB
Stitchable PCBs (no room for cables)
Feasability prototypes in fab
1.5m
Glue ? Solder ?
PCB type 1
PCB type 2
PCB type 3

9. Front-end chip R&D

10. Requirements for FEE Ultra-low dissipation (100µW/ch) involves :
Self-triggered ASIC : Zero-suppress on the chip
On chip A/D conversion and memory to buffer outputed data
Ultra-thin design involves :
Stand-alone ASIC : no room for decoupling capacitance
Huge number of channels involves :
System on Chip : all features have to be integrated
Calibration, ADC, analogue memory, digital memory, BCID, back-end bus, etc.
 Chip output : digital formated data

11. Power comsumption & integration
The critical issue : power consumption
ATLAS FEB 1W/Ch
400*500mm
FLC physic proto 5mW/Ch
10*10mm
ILC 100µW/Ch
2010

12. Power flexing : pulsed electronic
Based on TESLA TDR
Time between two trains: 200ms (5 Hz)
time
Time between two bunch crossing: 337 ns
Train length bunch X (950 us)
A/D conv.
DAQ
IDLE MODE
Acquisition
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
199ms (99%)
99% duty cycle
1% duty cycle
 See ILC_PHY4 results

13. On chip formated data  32bits / event without Chip ID
Channel nb - 6 bit
ADC result - 12 bit
Chip ID - x bit
BCID – 12 bit
Gain - 2 bit
Position
Energy
Time
 32bits / event without Chip ID

14. Data rates Assuming TESLA like bunch structure Raw Data volume
Bunch crossing period within bunch train = 176ns ~ 200ns
Number of crossings per bunch train = 4886 ~ 5000
Bunch train length = 860µs ~ 1ms
Bunch train period =250ms ~ 200ms
Raw Data volume
2 bytes Energy data/Channel, 20 Million channels
Raw data per bunch train ~ 20M  5000  2 ~ 200GBytes ECAL
No way to digitize inside the ~ ms train
10 kbytes/channel/train ~ 50 kbytes/ch/s
Physics data rate : 90 Mbytes/train = ~20 bytes/ch/s
Zero suppression mandatory
103 rate reduction -> drastic for power dissipation
Digitize only signals over 1/2MIP with noise < MIP/10
Allow storage in front-end ASIC

15. R&D building blocks

16. High dynamic range structure
Low noise charge preamp
3 integration shaper (G. 2, 20 & 100)

17. Measurement (Oscilloscope)
Functionaality test
Simulation
Measurement (Oscilloscope)
Gain 100
Gain 20
Gain 2

18. Linearity measurement
Gain 2 : NL 4‰
Gain 20 : NL 4‰
Gain 100 : NL 7‰

19. Pipeline ADC 10 bits ADC → 10 stages
Vin b1 b2 b3 b4 b5 b6 b7
b10 b9 b8
Amplifier
Gain=2
To VIN stage N+1
Vref
VIN
Gnd
Comparator
Bit N out
Vref
Stage N of pipeline ADC block schema

20. Pipeline ADC measurement
Gain : instead of 2
Offset : 18mV (cumulated)
1.5 bit/stage correction
integral non linearity ±2 LSB

21. ILC_PHY4 : a first step toward final ASIC
18 channels
Multi gain charge preamp (167mV/pC 2.5V/pC)
Dual shaper gain 1&10
2 track and hold
Switchable calibration injection capacitance
2 analogue multiplexers 181
One for gain 1 and one for gain 10
The two MUX output are MUX to a single output
1 ADC – 12 bit / 1MSPS – IP from AMS (founder)
An internal bias device including :
Internal decoupling on current sources
Idle mode on whole analogue parts of the chip

22. ILC_PHY4 layout & status
Chip produced & packaged
Test board produced
Missing test board firmware
Ready before summer
Test to be performed April/May 06
12 bits ADC IP

23. Power pulsing on ILC_PHY4
Tested on a stand-alone preamp
Switching from idle current (i/1000) to nominal
On-setting time < 20 µs
Pulse amplitude and noise identical in pulsed mode than in steady mode
Allows to reduce power by 99% with beams 2ms/200ms
Target power of 100 µW/channel appears within reach : to be validated in testbeam in 2006 with ILC_PHY4 ASIC
RFCF
signal
Log scales ! ON
20 µs
Ready for pulse

24. Schedule
Multi channel prototype foundry planned in spring06 including :
Analogue front-end
Power pulsed
Self-biased
Self-trigger
Pipeline ADC (LPCC)
Stitchable PCB planned for october06

25. Conclusions
CALICE collaboration help by EUDET (european funding) will built a technological prototype as close as possible to the final detector.
That technological prototype will validate the feasibility of the full detector
Many ASIC R&D are performed to have all the building blocks before the end of the year
Thin stitchible PCBs are currently in design.

26. Spare slides

27. Test plans

28. Front-end ASIC in a EM shower
Summer with FLC_PHY3 + FEV3

29. A/D conversion on chip ILC_PHY4 test to check mixed chip performance
New foundry LPC+LAL with LPC 12-bit pipeline ADC