Performed by: Borzin Artyom Lapchev Stas Instructor: Brodny Hen Cooperated with: Magnifire Ltd. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Subject: Spring

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 The Proxy Cache Engine board achieves its assignments by performing fast and effective main memory management. This system stores the information about the mapping of all files in main memory and calculates the exact path to required chunk if it is present in main memory or orders the operation system to bring it from the storage device. If the file was not found, the path to the free memory space is supplied. In contrast to any software solution, the hardware device can perform the associative search, which contributes a lot to the whole system performance.

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 In standard network system, the client sends its request to the server to bring a new page to his/her computer. The user request contains, amount other parameters, the logical path to the file, which is to be loaded on his/her computer. Current configuration assumes that this path is a string of up to 512 characters. This path is sent to the Proxy Cache Engine that replies with the index of the page location in main memory. If the page is not in main memory, the response contains the path to unused main memory space, where the page is to be loaded.

System description(cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The Proxy Cache Engine supports up to 2Mega paths in main memory. The mapping of the original path (512 bytes) to the physical path (2Mega combinations) is done by CRC (Cyclic Redundancy Check) algorithm. This encrypting method provides an approximation to fully associative main memory usage. In spite of non-unique translation of ~100 string combinations to 2 addresses, the probability of collision is quite low. Each loaded to main memory file has its aging parameters, which are defined by the application. The TTL parameter defines the minimum time (in minutes) of a file to stay in main memory. The Weight value reflects the hit rate statistics. It is incremented on each hit and is decremented as the time passes.

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Altera FLEX device 9054 PLX based PCI controller SSRAM 2Mb SDRAM 128 MB UTCAM engine Graphic User Interface Device Driver

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 PLX PCI9054 ALTERA FPGA Aeroflex UTCAM Engine Micron SDRAM Module (128Mbyte) Micron SSRAM (2x2Mbit) Micron SSRAM (2x2Mbit)

FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Local Bus Interface Decoder Database manager CRC unit CS Fix block UTCAM Engine Local Bus Registers UTCAM Engine SDRAM SSRAM